From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Ben Zong-You Xie <ben717@andestech.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, tglx@linutronix.de,
prabhakar.mahadev-lad.rj@bp.renesas.com, geert+renesas@glider.be,
magnus.damm@gmail.com, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
tim609@andestech.com, Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v4 5/9] dt-bindings: timer: add Andes machine timer
Date: Wed, 14 May 2025 17:21:10 +0200 [thread overview]
Message-ID: <aCS05j9ZYqga6dIO@mai.linaro.org> (raw)
In-Reply-To: <20250514095350.3765716-6-ben717@andestech.com>
On Wed, May 14, 2025 at 05:53:46PM +0800, Ben Zong-You Xie wrote:
> Add the DT binding documentation for Andes machine timer.
>
> The RISC-V architecture defines a machine timer that provides a real-time
> counter and generates timer interrupts. Andes machiner timer (PLMT0) is
> the implementation of the machine timer, and it contains memory-mapped
> registers (mtime and mtimecmp). This device supports up to 32 cores.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
The patch does not apply on my tree due to conflict with other patches
of the series on the MAINTAINER file.
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next prev parent reply other threads:[~2025-05-14 16:09 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 9:53 [PATCH v4 0/9] add Voyager board support Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-14 14:53 ` Rob Herring (Arm)
2025-05-14 15:01 ` Rob Herring
2025-05-15 3:25 ` Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-14 15:01 ` Rob Herring
2025-05-15 3:12 ` Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-14 15:21 ` Daniel Lezcano [this message]
2025-05-14 9:53 ` [PATCH v4 6/9] dt-bindings: cache: add QiLai compatible to ax45mp Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-05-14 9:53 ` [PATCH v4 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
2025-05-14 15:53 ` (subset) [PATCH v4 0/9] add Voyager board support Conor Dooley
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