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Mon, 19 May 2025 16:32:04 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:5f9c:a71e:a2da:158d]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eb0a9893sm6875885a12.72.2025.05.19.16.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 16:32:03 -0700 (PDT) Date: Mon, 19 May 2025 16:32:01 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function Message-ID: References: <20250515082217.433227-1-cleger@rivosinc.com> <20250515082217.433227-10-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250515082217.433227-10-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250519_163206_067427_24FD435B X-CRM114-Status: GOOD ( 21.32 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 15, 2025 at 10:22:10AM +0200, Cl=E9ment L=E9ger wrote: > Split the code that check for the uniformity of misaligned accesses > performance on all cpus from check_unaligned_access_emulated_all_cpus() > to its own function which will be used for delegation check. No > functional changes intended. > = > Signed-off-by: Cl=E9ment L=E9ger > Reviewed-by: Andrew Jones > --- > arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) > = > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index e551ba17f557..287ec37021c8 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -647,6 +647,18 @@ bool __init check_vector_unaligned_access_emulated_a= ll_cpus(void) > } > #endif > = > +static bool all_cpus_unaligned_scalar_access_emulated(void) > +{ > + int cpu; > + > + for_each_online_cpu(cpu) > + if (per_cpu(misaligned_access_speed, cpu) !=3D misaligned_access_speed is only defined when CONFIG_RISCV_SCALAR_MISALIGNED. This function should return false when !CONFIG_RISCV_SCALAR_MISALIGNED and only use this logic otherwise. - Charlie > + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > + return false; > + > + return true; > +} > + > #ifdef CONFIG_RISCV_SCALAR_MISALIGNED > = > static bool unaligned_ctl __read_mostly; > @@ -685,8 +697,6 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) > = > bool __init check_unaligned_access_emulated_all_cpus(void) > { > - int cpu; > - > /* > * We can only support PR_UNALIGN controls if all CPUs have misaligned > * accesses emulated since tasks requesting such control can run on any > @@ -694,10 +704,8 @@ bool __init check_unaligned_access_emulated_all_cpus= (void) > */ > on_each_cpu(check_unaligned_access_emulated, NULL, 1); > = > - for_each_online_cpu(cpu) > - if (per_cpu(misaligned_access_speed, cpu) > - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > - return false; > + if (!all_cpus_unaligned_scalar_access_emulated()) > + return false; > = > unaligned_ctl =3D true; > return true; > -- = > 2.49.0 > = > = > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv