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Tue, 20 May 2025 10:08:22 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:17b4:8663:3229:f2dd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b26eaf96573sm8189882a12.43.2025.05.20.10.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 May 2025 10:08:21 -0700 (PDT) Date: Tue, 20 May 2025 10:08:19 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function Message-ID: References: <20250515082217.433227-1-cleger@rivosinc.com> <20250515082217.433227-10-cleger@rivosinc.com> <126762fc-17ca-4e9d-94d0-3aed1ae321ff@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <126762fc-17ca-4e9d-94d0-3aed1ae321ff@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250520_100823_426389_2D67D096 X-CRM114-Status: GOOD ( 36.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, May 20, 2025 at 10:19:47AM +0200, Cl=E9ment L=E9ger wrote: > = > = > On 20/05/2025 01:32, Charlie Jenkins wrote: > > On Thu, May 15, 2025 at 10:22:10AM +0200, Cl=E9ment L=E9ger wrote: > >> Split the code that check for the uniformity of misaligned accesses > >> performance on all cpus from check_unaligned_access_emulated_all_cpus() > >> to its own function which will be used for delegation check. No > >> functional changes intended. > >> > >> Signed-off-by: Cl=E9ment L=E9ger > >> Reviewed-by: Andrew Jones > >> --- > >> arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------ > >> 1 file changed, 14 insertions(+), 6 deletions(-) > >> > >> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/= traps_misaligned.c > >> index e551ba17f557..287ec37021c8 100644 > >> --- a/arch/riscv/kernel/traps_misaligned.c > >> +++ b/arch/riscv/kernel/traps_misaligned.c > >> @@ -647,6 +647,18 @@ bool __init check_vector_unaligned_access_emulate= d_all_cpus(void) > >> } > >> #endif > >> = > >> +static bool all_cpus_unaligned_scalar_access_emulated(void) > >> +{ > >> + int cpu; > >> + > >> + for_each_online_cpu(cpu) > >> + if (per_cpu(misaligned_access_speed, cpu) !=3D > > = > > misaligned_access_speed is only defined when > > CONFIG_RISCV_SCALAR_MISALIGNED. This function should return false when > > !CONFIG_RISCV_SCALAR_MISALIGNED and only use this logic otherwise. > = > Hi Charlie, > = > misaligned_access_speed is defined in unaligned_access_speed.c which is > compiled based on CONFIG_RISCV_MISALIGNED (ditto for trap_misaligned.c) > = > obj-$(CONFIG_RISCV_MISALIGNED) +=3D unaligned_access_speed.o > = > However, the declaration for it in the header cpu-feature.h however is > under a CONFIG_RISCV_SCALAR_MISALIGNED ifdef. So either the declaration > or the definition is wrong but the ifdefery soup makes it quite > difficult to understand what's going on. > = > I would suggest to move the DECLARE_PER_CPU under > CONFIG_RISCV_MISALIGNED so that it reduces ifdef in traps_misaligned as > well. Here is the patch I am using locally for testing purposes, but if there is a way to reduce the number of ifdefs that is probably the better way to = go: >From 18f9a056d3b597934c931abdf72fb6e775ccb714 Mon Sep 17 00:00:00 2001 From: Charlie Jenkins Date: Mon, 19 May 2025 16:35:51 -0700 Subject: [PATCH] fixup! riscv: misaligned: move emulated access uniformity check in a function --- arch/riscv/kernel/traps_misaligned.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index f3ab84bc4632..1449c6a4ac21 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -647,6 +647,10 @@ bool __init check_vector_unaligned_access_emulated_all= _cpus(void) } #endif = +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED + +static bool unaligned_ctl __read_mostly; + static bool all_cpus_unaligned_scalar_access_emulated(void) { int cpu; @@ -659,10 +663,6 @@ static bool all_cpus_unaligned_scalar_access_emulated(= void) return true; } = -#ifdef CONFIG_RISCV_SCALAR_MISALIGNED - -static bool unaligned_ctl __read_mostly; - static void check_unaligned_access_emulated(void *arg __always_unused) { int cpu =3D smp_processor_id(); @@ -716,6 +716,10 @@ bool unaligned_ctl_available(void) return unaligned_ctl; } #else +static bool all_cpus_unaligned_scalar_access_emulated(void) +{ + return false; +} bool __init check_unaligned_access_emulated_all_cpus(void) { return false; -- = 2.43.0 - Charlie > = > Thanks, > > Cl=E9ment > = > > = > > - Charlie > > = > >> + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > >> + return false; > >> + > >> + return true; > >> +} > >> + > >> #ifdef CONFIG_RISCV_SCALAR_MISALIGNED > >> = > >> static bool unaligned_ctl __read_mostly; > >> @@ -685,8 +697,6 @@ static int cpu_online_check_unaligned_access_emula= ted(unsigned int cpu) > >> = > >> bool __init check_unaligned_access_emulated_all_cpus(void) > >> { > >> - int cpu; > >> - > >> /* > >> * We can only support PR_UNALIGN controls if all CPUs have misalign= ed > >> * accesses emulated since tasks requesting such control can run on = any > >> @@ -694,10 +704,8 @@ bool __init check_unaligned_access_emulated_all_c= pus(void) > >> */ > >> on_each_cpu(check_unaligned_access_emulated, NULL, 1); > >> = > >> - for_each_online_cpu(cpu) > >> - if (per_cpu(misaligned_access_speed, cpu) > >> - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > >> - return false; > >> + if (!all_cpus_unaligned_scalar_access_emulated()) > >> + return false; > >> = > >> unaligned_ctl =3D true; > >> return true; > >> -- = > >> 2.49.0 > >> > >> > >> _______________________________________________ > >> linux-riscv mailing list > >> linux-riscv@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-riscv > = _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv