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Fri, 06 Jun 2025 09:58:18 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236032ff216sm14585925ad.111.2025.06.06.09.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 09:58:18 -0700 (PDT) Date: Fri, 6 Jun 2025 09:58:16 -0700 From: Deepak Gupta To: Chunyan Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Morton , Alexandre Ghiti , Ved Shanbhogue , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: Re: [PATCH RFC v7 1/3] riscv: Add RISC-V Svrsw60t59b extension support Message-ID: References: <20250409095320.224100-1-zhangchunyan@iscas.ac.cn> <20250409095320.224100-2-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250409095320.224100-2-zhangchunyan@iscas.ac.cn> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250606_095819_846320_A76D9363 X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 09, 2025 at 05:53:18PM +0800, Chunyan Zhang wrote: >The Svrsw60t59b extension allows to free the PTE reserved bits 60 >and 59 for software to use. > >Signed-off-by: Chunyan Zhang >--- > arch/riscv/Kconfig | 13 +++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 15 insertions(+) > >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >index bbec87b79309..332fc00243ad 100644 >--- a/arch/riscv/Kconfig >+++ b/arch/riscv/Kconfig >@@ -842,6 +842,19 @@ config RISCV_ISA_ZICBOZ > > If you don't know what to do here, say Y. > >+config RISCV_ISA_SVRSW60T59B >+ bool "Svrsw60t59b extension support for using PTE bits 60 and 59" >+ depends on RISCV_ALTERNATIVE depends on MMU && 64BIT as well. >+ default y >+ help >+ Adds support to dynamically detect the presence of the SVRSW60T59B >+ extension and enable its usage. >+ >+ The Svrsw60t59b extension allows to free the PTE reserved bits 60 >+ and 59 for software to use. >+ >+ If you don't know what to do here, say Y. >+ > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI > def_bool y > # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >index e3cbf203cdde..985f6dfc80ed 100644 >--- a/arch/riscv/include/asm/hwcap.h >+++ b/arch/riscv/include/asm/hwcap.h >@@ -105,6 +105,7 @@ > #define RISCV_ISA_EXT_ZVFBFWMA 96 > #define RISCV_ISA_EXT_ZAAMO 97 > #define RISCV_ISA_EXT_ZALRSC 98 >+#define RISCV_ISA_EXT_SVRSW60T59B 99 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 2054f6c4b0ae..0f0f3027d400 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -523,6 +523,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), >+ __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B), > }; > > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); >-- >2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv