[PATCH RFC v7 0/3] riscv: mm: Add soft-dirty and uffd-wp support

[PATCH RFC v7 0/3] riscv: mm: Add soft-dirty and uffd-wp support

[Chunyan Zhang]

This patchset adds soft dirty and userfaultfd write protect tracking 
support for RISC-V.

This patchset has been tested with kselftest mm suite in which soft-dirty, 
madv_populate, test_unmerge_uffd_wp, and uffd-unit-tests run and pass,
and no regressions are observed in any of the other tests.

This patchset applies on top of v6.15-rc1.

V7:
- Add Svrsw60t59b [1] extension support;
- Have soft-dirty and uffd-wp depending on the Svrsw60t59b extension to
  avoid crashes for the hardware which don't have this extension.

V6:
- Changes to use bits 59-60 which are supported by extension Svrsw60t59b
  for soft dirty and userfaultfd write protect tracking.

V5:
- Fixed typos and corrected some words in Kconfig and commit message;
- Removed pte_wrprotect() from pte_swp_mkuffd_wp(), this is a copy-paste
  error;
- Added Alex's Reviewed-by tag in patch 2.

V4:
- Added bit(4) descriptions into "Format of swap PTE".

V3:
- Fixed the issue reported by kernel test irobot <lkp@intel.com>.

V1 -> V2:
- Add uffd-wp supported;
- Make soft-dirty uffd-wp and devmap mutually exclusive which all use
  the same PTE bit;
- Add test results of CRIU in the cover-letter.

[1] https://github.com/riscv/Svrsw60t59b.git

Chunyan Zhang (3):
  riscv: Add RISC-V Svrsw60t59b extension support
  riscv: mm: Add soft-dirty page tracking support
  riscv: mm: Add uffd write-protect support

 arch/riscv/Kconfig                    |  15 +++
 arch/riscv/include/asm/hwcap.h        |   1 +
 arch/riscv/include/asm/pgtable-bits.h |  37 +++++++
 arch/riscv/include/asm/pgtable.h      | 136 +++++++++++++++++++++++++-
 arch/riscv/kernel/cpufeature.c        |   1 +
 5 files changed, 188 insertions(+), 2 deletions(-)

-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH RFC v7 1/3] riscv: Add RISC-V Svrsw60t59b extension support

[Chunyan Zhang]

The Svrsw60t59b extension allows to free the PTE reserved bits 60
and 59 for software to use.

Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
 arch/riscv/Kconfig             | 13 +++++++++++++
 arch/riscv/include/asm/hwcap.h |  1 +
 arch/riscv/kernel/cpufeature.c |  1 +
 3 files changed, 15 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index bbec87b79309..332fc00243ad 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -842,6 +842,19 @@ config RISCV_ISA_ZICBOZ
 
 	   If you don't know what to do here, say Y.
 
+config RISCV_ISA_SVRSW60T59B
+	bool "Svrsw60t59b extension support for using PTE bits 60 and 59"
+	depends on RISCV_ALTERNATIVE
+	default y
+	help
+	  Adds support to dynamically detect the presence of the SVRSW60T59B
+	  extension and enable its usage.
+
+	  The Svrsw60t59b extension allows to free the PTE reserved bits 60
+	  and 59 for software to use.
+
+	  If you don't know what to do here, say Y.
+
 config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
 	def_bool y
 	# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index e3cbf203cdde..985f6dfc80ed 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -105,6 +105,7 @@
 #define RISCV_ISA_EXT_ZVFBFWMA		96
 #define RISCV_ISA_EXT_ZAAMO		97
 #define RISCV_ISA_EXT_ZALRSC		98
+#define RISCV_ISA_EXT_SVRSW60T59B	99
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 2054f6c4b0ae..0f0f3027d400 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -523,6 +523,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
 	__RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
+	__RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
 };
 
 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 1/3] riscv: Add RISC-V Svrsw60t59b extension support

[Deepak Gupta]

On Wed, Apr 09, 2025 at 05:53:18PM +0800, Chunyan Zhang wrote:
>The Svrsw60t59b extension allows to free the PTE reserved bits 60
>and 59 for software to use.
>
>Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>---
> arch/riscv/Kconfig             | 13 +++++++++++++
> arch/riscv/include/asm/hwcap.h |  1 +
> arch/riscv/kernel/cpufeature.c |  1 +
> 3 files changed, 15 insertions(+)
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>index bbec87b79309..332fc00243ad 100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -842,6 +842,19 @@ config RISCV_ISA_ZICBOZ
>
> 	   If you don't know what to do here, say Y.
>
>+config RISCV_ISA_SVRSW60T59B
>+	bool "Svrsw60t59b extension support for using PTE bits 60 and 59"
>+	depends on RISCV_ALTERNATIVE

depends on MMU && 64BIT as well.

>+	default y
>+	help
>+	  Adds support to dynamically detect the presence of the SVRSW60T59B
>+	  extension and enable its usage.
>+
>+	  The Svrsw60t59b extension allows to free the PTE reserved bits 60
>+	  and 59 for software to use.
>+
>+	  If you don't know what to do here, say Y.
>+
> config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
> 	def_bool y
> 	# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
>diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>index e3cbf203cdde..985f6dfc80ed 100644
>--- a/arch/riscv/include/asm/hwcap.h
>+++ b/arch/riscv/include/asm/hwcap.h
>@@ -105,6 +105,7 @@
> #define RISCV_ISA_EXT_ZVFBFWMA		96
> #define RISCV_ISA_EXT_ZAAMO		97
> #define RISCV_ISA_EXT_ZALRSC		98
>+#define RISCV_ISA_EXT_SVRSW60T59B	99
>
> #define RISCV_ISA_EXT_XLINUXENVCFG	127
>
>diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>index 2054f6c4b0ae..0f0f3027d400 100644
>--- a/arch/riscv/kernel/cpufeature.c
>+++ b/arch/riscv/kernel/cpufeature.c
>@@ -523,6 +523,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> 	__RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
>+	__RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
> };
>
> const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
>-- 
>2.34.1
>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 1/3] riscv: Add RISC-V Svrsw60t59b extension support

[Chunyan Zhang]

Hi Deepak,

On Sat, 7 Jun 2025 at 00:58, Deepak Gupta <debug@rivosinc.com> wrote:
>
> On Wed, Apr 09, 2025 at 05:53:18PM +0800, Chunyan Zhang wrote:
> >The Svrsw60t59b extension allows to free the PTE reserved bits 60
> >and 59 for software to use.
> >
> >Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> >---
> > arch/riscv/Kconfig             | 13 +++++++++++++
> > arch/riscv/include/asm/hwcap.h |  1 +
> > arch/riscv/kernel/cpufeature.c |  1 +
> > 3 files changed, 15 insertions(+)
> >
> >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >index bbec87b79309..332fc00243ad 100644
> >--- a/arch/riscv/Kconfig
> >+++ b/arch/riscv/Kconfig
> >@@ -842,6 +842,19 @@ config RISCV_ISA_ZICBOZ
> >
> >          If you don't know what to do here, say Y.
> >
> >+config RISCV_ISA_SVRSW60T59B
> >+      bool "Svrsw60t59b extension support for using PTE bits 60 and 59"
> >+      depends on RISCV_ALTERNATIVE
>
> depends on MMU && 64BIT as well.

Ok, I will address in the next version.

Thanks for the review,
Chunyan

>
> >+      default y
> >+      help
> >+        Adds support to dynamically detect the presence of the SVRSW60T59B
> >+        extension and enable its usage.
> >+
> >+        The Svrsw60t59b extension allows to free the PTE reserved bits 60
> >+        and 59 for software to use.
> >+
> >+        If you don't know what to do here, say Y.
> >+
> > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
> >       def_bool y
> >       # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
> >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> >index e3cbf203cdde..985f6dfc80ed 100644
> >--- a/arch/riscv/include/asm/hwcap.h
> >+++ b/arch/riscv/include/asm/hwcap.h
> >@@ -105,6 +105,7 @@
> > #define RISCV_ISA_EXT_ZVFBFWMA                96
> > #define RISCV_ISA_EXT_ZAAMO           97
> > #define RISCV_ISA_EXT_ZALRSC          98
> >+#define RISCV_ISA_EXT_SVRSW60T59B     99
> >
> > #define RISCV_ISA_EXT_XLINUXENVCFG    127
> >
> >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >index 2054f6c4b0ae..0f0f3027d400 100644
> >--- a/arch/riscv/kernel/cpufeature.c
> >+++ b/arch/riscv/kernel/cpufeature.c
> >@@ -523,6 +523,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> >       __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> >       __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
> >+      __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
> > };
> >
> > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> >--
> >2.34.1
> >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 1/3] riscv: Add RISC-V Svrsw60t59b extension support

[Alexandre Ghiti]

Hi Chunyan,

On 6/12/25 08:48, Chunyan Zhang wrote:
> Hi Deepak,
>
> On Sat, 7 Jun 2025 at 00:58, Deepak Gupta <debug@rivosinc.com> wrote:
>> On Wed, Apr 09, 2025 at 05:53:18PM +0800, Chunyan Zhang wrote:
>>> The Svrsw60t59b extension allows to free the PTE reserved bits 60
>>> and 59 for software to use.
>>>
>>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>>> ---
>>> arch/riscv/Kconfig             | 13 +++++++++++++
>>> arch/riscv/include/asm/hwcap.h |  1 +
>>> arch/riscv/kernel/cpufeature.c |  1 +
>>> 3 files changed, 15 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>> index bbec87b79309..332fc00243ad 100644
>>> --- a/arch/riscv/Kconfig
>>> +++ b/arch/riscv/Kconfig
>>> @@ -842,6 +842,19 @@ config RISCV_ISA_ZICBOZ
>>>
>>>           If you don't know what to do here, say Y.
>>>
>>> +config RISCV_ISA_SVRSW60T59B
>>> +      bool "Svrsw60t59b extension support for using PTE bits 60 and 59"
>>> +      depends on RISCV_ALTERNATIVE
>> depends on MMU && 64BIT as well.
> Ok, I will address in the next version.
>
> Thanks for the review,
> Chunyan
>
>>> +      default y
>>> +      help
>>> +        Adds support to dynamically detect the presence of the SVRSW60T59B


s/SVRSW60T59B/Svrsw60t59b

You can add:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alexandre Ghiti


>>> +        extension and enable its usage.
>>> +
>>> +        The Svrsw60t59b extension allows to free the PTE reserved bits 60
>>> +        and 59 for software to use.
>>> +
>>> +        If you don't know what to do here, say Y.
>>> +
>>> config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
>>>        def_bool y
>>>        # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
>>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>>> index e3cbf203cdde..985f6dfc80ed 100644
>>> --- a/arch/riscv/include/asm/hwcap.h
>>> +++ b/arch/riscv/include/asm/hwcap.h
>>> @@ -105,6 +105,7 @@
>>> #define RISCV_ISA_EXT_ZVFBFWMA                96
>>> #define RISCV_ISA_EXT_ZAAMO           97
>>> #define RISCV_ISA_EXT_ZALRSC          98
>>> +#define RISCV_ISA_EXT_SVRSW60T59B     99
>>>
>>> #define RISCV_ISA_EXT_XLINUXENVCFG    127
>>>
>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>>> index 2054f6c4b0ae..0f0f3027d400 100644
>>> --- a/arch/riscv/kernel/cpufeature.c
>>> +++ b/arch/riscv/kernel/cpufeature.c
>>> @@ -523,6 +523,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>>>        __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
>>>        __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
>>>        __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
>>> +      __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
>>> };
>>>
>>> const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
>>> --
>>> 2.34.1
>>>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH RFC v7 2/3] riscv: mm: Add soft-dirty page tracking support

[Chunyan Zhang]

The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software, this patch uses bit 59 for soft-dirty.

To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
for swap PTEs on RISC-V systems.

Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
 arch/riscv/Kconfig                    |  1 +
 arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
 arch/riscv/include/asm/pgtable.h      | 71 ++++++++++++++++++++++++++-
 3 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 332fc00243ad..652e2bbfb702 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -139,6 +139,7 @@ config RISCV
 	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
 	select HAVE_ARCH_SECCOMP_FILTER
+	select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
 	select HAVE_ARCH_STACKLEAK
 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 	select HAVE_ARCH_TRACEHOOK
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a8f5205cea54..a6fa871dc19e 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -20,6 +20,25 @@
 
 #define _PAGE_SPECIAL   (1 << 8)    /* RSW: 0x1 */
 #define _PAGE_DEVMAP    (1 << 9)    /* RSW, devmap */
+
+#ifdef CONFIG_MEM_SOFT_DIRTY
+
+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
+#define _PAGE_SOFT_DIRTY						\
+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
+	 (1UL << 59) : 0)
+/*
+ * Bit 3 is always zero for swap entry computation, so we
+ * can borrow it for swap page soft-dirty tracking.
+ */
+#define _PAGE_SWP_SOFT_DIRTY						\
+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
+	 _PAGE_EXEC : 0)
+#else
+#define _PAGE_SOFT_DIRTY	0
+#define _PAGE_SWP_SOFT_DIRTY	0
+#endif /* CONFIG_MEM_SOFT_DIRTY */
+
 #define _PAGE_TABLE     _PAGE_PRESENT
 
 /*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 428e48e5f57d..14461ffe6321 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -436,7 +436,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
 
 static inline pte_t pte_mkdirty(pte_t pte)
 {
-	return __pte(pte_val(pte) | _PAGE_DIRTY);
+	return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
 }
 
 static inline pte_t pte_mkclean(pte_t pte)
@@ -469,6 +469,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
 	return pte;
 }
 
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline bool pte_soft_dirty(pte_t pte)
+{
+	return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
+}
+
+static inline pte_t pte_mksoft_dirty(pte_t pte)
+{
+	return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
+}
+
+static inline pte_t pte_clear_soft_dirty(pte_t pte)
+{
+	return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
+}
+
+static inline bool pte_swp_soft_dirty(pte_t pte)
+{
+	return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
+}
+
+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
+{
+	return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
+}
+
+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
+{
+	return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
+}
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
 #ifdef CONFIG_RISCV_ISA_SVNAPOT
 #define pte_leaf_size(pte)	(pte_napot(pte) ?				\
 					napot_cont_size(napot_cont_order(pte)) :\
@@ -821,6 +853,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
 }
 #endif
 
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline bool pmd_soft_dirty(pmd_t pmd)
+{
+	return pte_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
+{
+	return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
+{
+	return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
+}
+
+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
+static inline bool pmd_swp_soft_dirty(pmd_t pmd)
+{
+	return pte_swp_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
+{
+	return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
+{
+	return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
+}
+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
 				pmd_t *pmdp, pmd_t pmd)
 {
@@ -910,7 +976,8 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
  *
  * Format of swap PTE:
  *	bit            0:	_PAGE_PRESENT (zero)
- *	bit       1 to 3:       _PAGE_LEAF (zero)
+ *	bit       1 to 2:	(zero)
+ *	bit            3:	_PAGE_SWP_SOFT_DIRTY
  *	bit            5:	_PAGE_PROT_NONE (zero)
  *	bit            6:	exclusive marker
  *	bits      7 to 11:	swap type
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 2/3] riscv: mm: Add soft-dirty page tracking support

[Deepak Gupta]

On Wed, Apr 09, 2025 at 05:53:19PM +0800, Chunyan Zhang wrote:
>The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
>for software, this patch uses bit 59 for soft-dirty.
>
>To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
>for swap PTEs on RISC-V systems.
>
>Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>---
> arch/riscv/Kconfig                    |  1 +
> arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
> arch/riscv/include/asm/pgtable.h      | 71 ++++++++++++++++++++++++++-
> 3 files changed, 89 insertions(+), 2 deletions(-)
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>index 332fc00243ad..652e2bbfb702 100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -139,6 +139,7 @@ config RISCV
> 	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
> 	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
> 	select HAVE_ARCH_SECCOMP_FILTER
>+	select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
> 	select HAVE_ARCH_STACKLEAK
> 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
> 	select HAVE_ARCH_TRACEHOOK
>diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>index a8f5205cea54..a6fa871dc19e 100644
>--- a/arch/riscv/include/asm/pgtable-bits.h
>+++ b/arch/riscv/include/asm/pgtable-bits.h
>@@ -20,6 +20,25 @@
>
> #define _PAGE_SPECIAL   (1 << 8)    /* RSW: 0x1 */
> #define _PAGE_DEVMAP    (1 << 9)    /* RSW, devmap */
>+
>+#ifdef CONFIG_MEM_SOFT_DIRTY
>+
>+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
>+#define _PAGE_SOFT_DIRTY						\
>+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
>+	 (1UL << 59) : 0)
>+/*
>+ * Bit 3 is always zero for swap entry computation, so we
>+ * can borrow it for swap page soft-dirty tracking.
>+ */
>+#define _PAGE_SWP_SOFT_DIRTY						\
>+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
>+	 _PAGE_EXEC : 0)
>+#else
>+#define _PAGE_SOFT_DIRTY	0
>+#define _PAGE_SWP_SOFT_DIRTY	0
>+#endif /* CONFIG_MEM_SOFT_DIRTY */
>+

Above can be done like this

+
+#ifdef CONFIG_MEM_SOFT_DIRTY && RISCV_ISA_EXT_SVRSW60T59B
+
+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
+#define _PAGE_SOFT_DIRTY (1UL << 59)
+/*
+ * Bit 3 is always zero for swap entry computation, so we
+ * can borrow it for swap page soft-dirty tracking.
+ */
+#define _PAGE_SWP_SOFT_DIRTY _PAGE_EXEC
+#else
+#define _PAGE_SOFT_DIRTY       0
+#define _PAGE_SWP_SOFT_DIRTY   0
+#endif /* CONFIG_MEM_SOFT_DIRTY */

> #define _PAGE_TABLE     _PAGE_PRESENT
>
> /*
>diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>index 428e48e5f57d..14461ffe6321 100644
>--- a/arch/riscv/include/asm/pgtable.h
>+++ b/arch/riscv/include/asm/pgtable.h
>@@ -436,7 +436,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)

Shouldn't "static inline int pte_dirty(pte_t pte)" be updated as well

static inline int pte_dirty(pte_t pte)
{
	return pte_val(pte) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY);
}

Perhaps have a macro which includes both dirty together and then use together.


>
> static inline pte_t pte_mkdirty(pte_t pte)
> {
>-	return __pte(pte_val(pte) | _PAGE_DIRTY);
>+	return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> static inline pte_t pte_mkclean(pte_t pte)
>@@ -469,6 +469,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> 	return pte;
> }
>
>+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>+static inline bool pte_soft_dirty(pte_t pte)
>+{
>+	return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
>+}
>+
>+static inline pte_t pte_mksoft_dirty(pte_t pte)
>+{
>+	return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>+}
>+
>+static inline pte_t pte_clear_soft_dirty(pte_t pte)
>+{
>+	return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>+}
>+
>+static inline bool pte_swp_soft_dirty(pte_t pte)
>+{
>+	return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
>+}
>+
>+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>+{
>+	return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>+}
>+
>+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>+{
>+	return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>+}
>+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>+
> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> #define pte_leaf_size(pte)	(pte_napot(pte) ?				\
> 					napot_cont_size(napot_cont_order(pte)) :\
>@@ -821,6 +853,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
> }
> #endif
>
>+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>+static inline bool pmd_soft_dirty(pmd_t pmd)
>+{
>+	return pte_soft_dirty(pmd_pte(pmd));
>+}
>+
>+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>+{
>+	return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>+}
>+
>+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>+{
>+	return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>+}
>+
>+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>+static inline bool pmd_swp_soft_dirty(pmd_t pmd)
>+{
>+	return pte_swp_soft_dirty(pmd_pte(pmd));
>+}
>+
>+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>+{
>+	return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>+}
>+
>+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>+{
>+	return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>+}
>+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>+
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> 				pmd_t *pmdp, pmd_t pmd)
> {
>@@ -910,7 +976,8 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>  *
>  * Format of swap PTE:
>  *	bit            0:	_PAGE_PRESENT (zero)
>- *	bit       1 to 3:       _PAGE_LEAF (zero)
>+ *	bit       1 to 2:	(zero)
>+ *	bit            3:	_PAGE_SWP_SOFT_DIRTY
>  *	bit            5:	_PAGE_PROT_NONE (zero)
>  *	bit            6:	exclusive marker
>  *	bits      7 to 11:	swap type
>-- 
>2.34.1
>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 2/3] riscv: mm: Add soft-dirty page tracking support

[Chunyan Zhang]

Hi Deepak,

On Sat, 7 Jun 2025 at 01:24, Deepak Gupta <debug@rivosinc.com> wrote:
>
> On Wed, Apr 09, 2025 at 05:53:19PM +0800, Chunyan Zhang wrote:
> >The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
> >for software, this patch uses bit 59 for soft-dirty.
> >
> >To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
> >for swap PTEs on RISC-V systems.
> >
> >Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> >---
> > arch/riscv/Kconfig                    |  1 +
> > arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
> > arch/riscv/include/asm/pgtable.h      | 71 ++++++++++++++++++++++++++-
> > 3 files changed, 89 insertions(+), 2 deletions(-)
> >
> >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >index 332fc00243ad..652e2bbfb702 100644
> >--- a/arch/riscv/Kconfig
> >+++ b/arch/riscv/Kconfig
> >@@ -139,6 +139,7 @@ config RISCV
> >       select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
> >       select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
> >       select HAVE_ARCH_SECCOMP_FILTER
> >+      select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
> >       select HAVE_ARCH_STACKLEAK
> >       select HAVE_ARCH_THREAD_STRUCT_WHITELIST
> >       select HAVE_ARCH_TRACEHOOK
> >diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> >index a8f5205cea54..a6fa871dc19e 100644
> >--- a/arch/riscv/include/asm/pgtable-bits.h
> >+++ b/arch/riscv/include/asm/pgtable-bits.h
> >@@ -20,6 +20,25 @@
> >
> > #define _PAGE_SPECIAL   (1 << 8)    /* RSW: 0x1 */
> > #define _PAGE_DEVMAP    (1 << 9)    /* RSW, devmap */
> >+
> >+#ifdef CONFIG_MEM_SOFT_DIRTY
> >+
> >+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
> >+#define _PAGE_SOFT_DIRTY                                              \
> >+      ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?    \
> >+       (1UL << 59) : 0)
> >+/*
> >+ * Bit 3 is always zero for swap entry computation, so we
> >+ * can borrow it for swap page soft-dirty tracking.
> >+ */
> >+#define _PAGE_SWP_SOFT_DIRTY                                          \
> >+      ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?    \
> >+       _PAGE_EXEC : 0)
> >+#else
> >+#define _PAGE_SOFT_DIRTY      0
> >+#define _PAGE_SWP_SOFT_DIRTY  0
> >+#endif /* CONFIG_MEM_SOFT_DIRTY */
> >+
>
> Above can be done like this
>
> +
> +#ifdef CONFIG_MEM_SOFT_DIRTY && RISCV_ISA_EXT_SVRSW60T59B
> +
> +/* ext_svrsw60t59b: bit 59 for software dirty tracking */
> +#define _PAGE_SOFT_DIRTY (1UL << 59)
> +/*
> + * Bit 3 is always zero for swap entry computation, so we
> + * can borrow it for swap page soft-dirty tracking.
> + */
> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_EXEC
> +#else
> +#define _PAGE_SOFT_DIRTY       0
> +#define _PAGE_SWP_SOFT_DIRTY   0
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>

No, the feature depends not only on the compile-time configuration but
also on the run-time environment.

We need to check if the platform on which the system is running
supports the extension SVRSW60T59B, and riscv_has_extension_unlikely()
does that check that is a run-time check, not a build-time condition.

> > #define _PAGE_TABLE     _PAGE_PRESENT
> >
> > /*
> >diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> >index 428e48e5f57d..14461ffe6321 100644
> >--- a/arch/riscv/include/asm/pgtable.h
> >+++ b/arch/riscv/include/asm/pgtable.h
> >@@ -436,7 +436,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>
> Shouldn't "static inline int pte_dirty(pte_t pte)" be updated as well

It may not be needed, since pte_dirty() on X86 and ARM doesn't check
_PAGE_SOFT_DIRTY either.

Thanks for the review,
Chunyan




>
> static inline int pte_dirty(pte_t pte)
> {
>         return pte_val(pte) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> Perhaps have a macro which includes both dirty together and then use together.
>
>
> >
> > static inline pte_t pte_mkdirty(pte_t pte)
> > {
> >-      return __pte(pte_val(pte) | _PAGE_DIRTY);
> >+      return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> > }
> >
> > static inline pte_t pte_mkclean(pte_t pte)
> >@@ -469,6 +469,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> >       return pte;
> > }
> >
> >+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> >+static inline bool pte_soft_dirty(pte_t pte)
> >+{
> >+      return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
> >+}
> >+
> >+static inline pte_t pte_mksoft_dirty(pte_t pte)
> >+{
> >+      return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> >+}
> >+
> >+static inline pte_t pte_clear_soft_dirty(pte_t pte)
> >+{
> >+      return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> >+}
> >+
> >+static inline bool pte_swp_soft_dirty(pte_t pte)
> >+{
> >+      return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
> >+}
> >+
> >+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> >+{
> >+      return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> >+}
> >+
> >+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> >+{
> >+      return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> >+}
> >+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> >+
> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
> > #define pte_leaf_size(pte)    (pte_napot(pte) ?                               \
> >                                       napot_cont_size(napot_cont_order(pte)) :\
> >@@ -821,6 +853,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
> > }
> > #endif
> >
> >+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> >+static inline bool pmd_soft_dirty(pmd_t pmd)
> >+{
> >+      return pte_soft_dirty(pmd_pte(pmd));
> >+}
> >+
> >+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> >+{
> >+      return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> >+}
> >+
> >+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> >+{
> >+      return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> >+}
> >+
> >+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> >+static inline bool pmd_swp_soft_dirty(pmd_t pmd)
> >+{
> >+      return pte_swp_soft_dirty(pmd_pte(pmd));
> >+}
> >+
> >+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> >+{
> >+      return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> >+}
> >+
> >+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> >+{
> >+      return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> >+}
> >+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> >+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> >+
> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> >                               pmd_t *pmdp, pmd_t pmd)
> > {
> >@@ -910,7 +976,8 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> >  *
> >  * Format of swap PTE:
> >  *    bit            0:       _PAGE_PRESENT (zero)
> >- *    bit       1 to 3:       _PAGE_LEAF (zero)
> >+ *    bit       1 to 2:       (zero)
> >+ *    bit            3:       _PAGE_SWP_SOFT_DIRTY
> >  *    bit            5:       _PAGE_PROT_NONE (zero)
> >  *    bit            6:       exclusive marker
> >  *    bits      7 to 11:      swap type
> >--
> >2.34.1
> >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 2/3] riscv: mm: Add soft-dirty page tracking support

[Deepak Gupta]

On Thu, Jun 12, 2025 at 02:51:57PM +0800, Chunyan Zhang wrote:
>Hi Deepak,
>
>On Sat, 7 Jun 2025 at 01:24, Deepak Gupta <debug@rivosinc.com> wrote:
>>
>> On Wed, Apr 09, 2025 at 05:53:19PM +0800, Chunyan Zhang wrote:
>> >The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
>> >for software, this patch uses bit 59 for soft-dirty.
>> >
>> >To add swap PTE soft-dirty tracking, we borrow bit 3 which is available
>> >for swap PTEs on RISC-V systems.
>> >
>> >Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>> >---
>> > arch/riscv/Kconfig                    |  1 +
>> > arch/riscv/include/asm/pgtable-bits.h | 19 +++++++
>> > arch/riscv/include/asm/pgtable.h      | 71 ++++++++++++++++++++++++++-
>> > 3 files changed, 89 insertions(+), 2 deletions(-)
>> >
>> >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> >index 332fc00243ad..652e2bbfb702 100644
>> >--- a/arch/riscv/Kconfig
>> >+++ b/arch/riscv/Kconfig
>> >@@ -139,6 +139,7 @@ config RISCV
>> >       select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
>> >       select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
>> >       select HAVE_ARCH_SECCOMP_FILTER
>> >+      select HAVE_ARCH_SOFT_DIRTY if 64BIT && MMU && RISCV_ISA_SVRSW60T59B
>> >       select HAVE_ARCH_STACKLEAK
>> >       select HAVE_ARCH_THREAD_STRUCT_WHITELIST
>> >       select HAVE_ARCH_TRACEHOOK
>> >diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>> >index a8f5205cea54..a6fa871dc19e 100644
>> >--- a/arch/riscv/include/asm/pgtable-bits.h
>> >+++ b/arch/riscv/include/asm/pgtable-bits.h
>> >@@ -20,6 +20,25 @@
>> >
>> > #define _PAGE_SPECIAL   (1 << 8)    /* RSW: 0x1 */
>> > #define _PAGE_DEVMAP    (1 << 9)    /* RSW, devmap */
>> >+
>> >+#ifdef CONFIG_MEM_SOFT_DIRTY
>> >+
>> >+/* ext_svrsw60t59b: bit 59 for software dirty tracking */
>> >+#define _PAGE_SOFT_DIRTY                                              \
>> >+      ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?    \
>> >+       (1UL << 59) : 0)
>> >+/*
>> >+ * Bit 3 is always zero for swap entry computation, so we
>> >+ * can borrow it for swap page soft-dirty tracking.
>> >+ */
>> >+#define _PAGE_SWP_SOFT_DIRTY                                          \
>> >+      ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?    \
>> >+       _PAGE_EXEC : 0)
>> >+#else
>> >+#define _PAGE_SOFT_DIRTY      0
>> >+#define _PAGE_SWP_SOFT_DIRTY  0
>> >+#endif /* CONFIG_MEM_SOFT_DIRTY */
>> >+
>>
>> Above can be done like this
>>
>> +
>> +#ifdef CONFIG_MEM_SOFT_DIRTY && RISCV_ISA_EXT_SVRSW60T59B
>> +
>> +/* ext_svrsw60t59b: bit 59 for software dirty tracking */
>> +#define _PAGE_SOFT_DIRTY (1UL << 59)
>> +/*
>> + * Bit 3 is always zero for swap entry computation, so we
>> + * can borrow it for swap page soft-dirty tracking.
>> + */
>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_EXEC
>> +#else
>> +#define _PAGE_SOFT_DIRTY       0
>> +#define _PAGE_SWP_SOFT_DIRTY   0
>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>>
>
>No, the feature depends not only on the compile-time configuration but
>also on the run-time environment.
>
>We need to check if the platform on which the system is running
>supports the extension SVRSW60T59B, and riscv_has_extension_unlikely()
>does that check that is a run-time check, not a build-time condition.
>

aah you are right. Ignore my comment.

>> > #define _PAGE_TABLE     _PAGE_PRESENT
>> >
>> > /*
>> >diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>> >index 428e48e5f57d..14461ffe6321 100644
>> >--- a/arch/riscv/include/asm/pgtable.h
>> >+++ b/arch/riscv/include/asm/pgtable.h
>> >@@ -436,7 +436,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>>
>> Shouldn't "static inline int pte_dirty(pte_t pte)" be updated as well
>
>It may not be needed, since pte_dirty() on X86 and ARM doesn't check
>_PAGE_SOFT_DIRTY either.

arch/arm64/include/asm/pgtable.h
#define pte_dirty(pte)		(pte_sw_dirty(pte) || pte_hw_dirty(pte))


`pte_sw_dirty` eventually expands to checking of b55 which is soft dirty.

But when I look at `pte_to_pagemap_entry` (`fs/proc/task_mmu.c`), I don't
see that pte to pagemap entry conversion for arm64. There is no equivalent
`pte_soft_dirty` macro defined on arm64.

Yeah may be it's not needed then.

>
>Thanks for the review,
>Chunyan
>
>
>
>
>>
>> static inline int pte_dirty(pte_t pte)
>> {
>>         return pte_val(pte) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>> }
>>
>> Perhaps have a macro which includes both dirty together and then use together.
>>
>>
>> >
>> > static inline pte_t pte_mkdirty(pte_t pte)
>> > {
>> >-      return __pte(pte_val(pte) | _PAGE_DIRTY);
>> >+      return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>> > }
>> >
>> > static inline pte_t pte_mkclean(pte_t pte)
>> >@@ -469,6 +469,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
>> >       return pte;
>> > }
>> >
>> >+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>> >+static inline bool pte_soft_dirty(pte_t pte)
>> >+{
>> >+      return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_mksoft_dirty(pte_t pte)
>> >+{
>> >+      return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_clear_soft_dirty(pte_t pte)
>> >+{
>> >+      return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>> >+}
>> >+
>> >+static inline bool pte_swp_soft_dirty(pte_t pte)
>> >+{
>> >+      return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>> >+{
>> >+      return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>> >+}
>> >+
>> >+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>> >+{
>> >+      return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>> >+}
>> >+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>> >+
>> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
>> > #define pte_leaf_size(pte)    (pte_napot(pte) ?                               \
>> >                                       napot_cont_size(napot_cont_order(pte)) :\
>> >@@ -821,6 +853,40 @@ static inline pud_t pud_mkspecial(pud_t pud)
>> > }
>> > #endif
>> >
>> >+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>> >+static inline bool pmd_soft_dirty(pmd_t pmd)
>> >+{
>> >+      return pte_soft_dirty(pmd_pte(pmd));
>> >+}
>> >+
>> >+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>> >+{
>> >+      return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>> >+}
>> >+
>> >+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>> >+{
>> >+      return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>> >+}
>> >+
>> >+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>> >+static inline bool pmd_swp_soft_dirty(pmd_t pmd)
>> >+{
>> >+      return pte_swp_soft_dirty(pmd_pte(pmd));
>> >+}
>> >+
>> >+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>> >+{
>> >+      return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>> >+}
>> >+
>> >+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>> >+{
>> >+      return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>> >+}
>> >+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>> >+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>> >+
>> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
>> >                               pmd_t *pmdp, pmd_t pmd)
>> > {
>> >@@ -910,7 +976,8 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>> >  *
>> >  * Format of swap PTE:
>> >  *    bit            0:       _PAGE_PRESENT (zero)
>> >- *    bit       1 to 3:       _PAGE_LEAF (zero)
>> >+ *    bit       1 to 2:       (zero)
>> >+ *    bit            3:       _PAGE_SWP_SOFT_DIRTY
>> >  *    bit            5:       _PAGE_PROT_NONE (zero)
>> >  *    bit            6:       exclusive marker
>> >  *    bits      7 to 11:      swap type
>> >--
>> >2.34.1
>> >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH RFC v7 3/3] riscv: mm: Add uffd write-protect support

[Chunyan Zhang]

The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software, this patch uses bit 60 for uffd-wp tracking

Additionally for tracking the uffd-wp state as a PTE swap bit, we borrow
bit 4 which is not involved into swap entry computation.

Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
 arch/riscv/Kconfig                    |  1 +
 arch/riscv/include/asm/pgtable-bits.h | 18 ++++++++
 arch/riscv/include/asm/pgtable.h      | 65 +++++++++++++++++++++++++++
 3 files changed, 84 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 652e2bbfb702..cafdfbe4412b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -145,6 +145,7 @@ config RISCV
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
 	select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
+	select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B
 	select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
 	select HAVE_ASM_MODVERSIONS
 	select HAVE_CONTEXT_TRACKING_USER
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a6fa871dc19e..a953a582cd75 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -39,6 +39,24 @@
 #define _PAGE_SWP_SOFT_DIRTY	0
 #endif /* CONFIG_MEM_SOFT_DIRTY */
 
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+
+/* ext_svrsw60t59b: Bit(60) for uffd-wp tracking */
+#define _PAGE_UFFD_WP							\
+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
+	 (1UL << 60) : 0)
+/*
+ * Bit 4 is not involved into swap entry computation, so we
+ * can borrow it for swap page uffd-wp tracking.
+ */
+#define _PAGE_SWP_UFFD_WP						\
+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
+	 _PAGE_USER : 0)
+#else
+#define _PAGE_UFFD_WP		0
+#define _PAGE_SWP_UFFD_WP	0
+#endif
+
 #define _PAGE_TABLE     _PAGE_PRESENT
 
 /*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 14461ffe6321..ee0fbca28a76 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -425,6 +425,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
 	return __pte(pte_val(pte) & ~(_PAGE_WRITE));
 }
 
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+static inline bool pte_uffd_wp(pte_t pte)
+{
+	return !!(pte_val(pte) & _PAGE_UFFD_WP);
+}
+
+static inline pte_t pte_mkuffd_wp(pte_t pte)
+{
+	return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
+}
+
+static inline pte_t pte_clear_uffd_wp(pte_t pte)
+{
+	return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
+}
+
+static inline bool pte_swp_uffd_wp(pte_t pte)
+{
+	return !!(pte_val(pte) & _PAGE_SWP_UFFD_WP);
+}
+
+static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
+{
+	return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP);
+}
+
+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
+{
+	return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
+}
+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
+
 /* static inline pte_t pte_mkread(pte_t pte) */
 
 static inline pte_t pte_mkwrite_novma(pte_t pte)
@@ -853,6 +885,38 @@ static inline pud_t pud_mkspecial(pud_t pud)
 }
 #endif
 
+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
+static inline bool pmd_uffd_wp(pmd_t pmd)
+{
+	return pte_uffd_wp(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
+{
+	return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
+{
+	return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
+}
+
+static inline bool pmd_swp_uffd_wp(pmd_t pmd)
+{
+	return pte_swp_uffd_wp(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
+{
+	return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
+{
+	return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
+}
+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
+
 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
 static inline bool pmd_soft_dirty(pmd_t pmd)
 {
@@ -978,6 +1042,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
  *	bit            0:	_PAGE_PRESENT (zero)
  *	bit       1 to 2:	(zero)
  *	bit            3:	_PAGE_SWP_SOFT_DIRTY
+ *	bit            4:	_PAGE_SWP_UFFD_WP
  *	bit            5:	_PAGE_PROT_NONE (zero)
  *	bit            6:	exclusive marker
  *	bits      7 to 11:	swap type
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH RFC v7 3/3] riscv: mm: Add uffd write-protect support

[Deepak Gupta]

On Wed, Apr 09, 2025 at 05:53:20PM +0800, Chunyan Zhang wrote:
>The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
>for software, this patch uses bit 60 for uffd-wp tracking
>
>Additionally for tracking the uffd-wp state as a PTE swap bit, we borrow
>bit 4 which is not involved into swap entry computation.
>
>Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>---
> arch/riscv/Kconfig                    |  1 +
> arch/riscv/include/asm/pgtable-bits.h | 18 ++++++++
> arch/riscv/include/asm/pgtable.h      | 65 +++++++++++++++++++++++++++
> 3 files changed, 84 insertions(+)
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>index 652e2bbfb702..cafdfbe4412b 100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -145,6 +145,7 @@ config RISCV
> 	select HAVE_ARCH_TRACEHOOK
> 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
> 	select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
>+	select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B
> 	select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
> 	select HAVE_ASM_MODVERSIONS
> 	select HAVE_CONTEXT_TRACKING_USER
>diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>index a6fa871dc19e..a953a582cd75 100644
>--- a/arch/riscv/include/asm/pgtable-bits.h
>+++ b/arch/riscv/include/asm/pgtable-bits.h
>@@ -39,6 +39,24 @@
> #define _PAGE_SWP_SOFT_DIRTY	0
> #endif /* CONFIG_MEM_SOFT_DIRTY */
>
>+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
>+
>+/* ext_svrsw60t59b: Bit(60) for uffd-wp tracking */
>+#define _PAGE_UFFD_WP							\
>+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
>+	 (1UL << 60) : 0)
>+/*
>+ * Bit 4 is not involved into swap entry computation, so we
>+ * can borrow it for swap page uffd-wp tracking.
>+ */
>+#define _PAGE_SWP_UFFD_WP						\
>+	((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ?	\
>+	 _PAGE_USER : 0)
>+#else
>+#define _PAGE_UFFD_WP		0
>+#define _PAGE_SWP_UFFD_WP	0
>+#endif
>+

Same comment as previous patch on above. Have `RISCV_ISA_EXT_SVRSW60T59B`
with the "#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP"


> #define _PAGE_TABLE     _PAGE_PRESENT
>
> /*
>diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>index 14461ffe6321..ee0fbca28a76 100644
>--- a/arch/riscv/include/asm/pgtable.h
>+++ b/arch/riscv/include/asm/pgtable.h
>@@ -425,6 +425,38 @@ static inline pte_t pte_wrprotect(pte_t pte)
> 	return __pte(pte_val(pte) & ~(_PAGE_WRITE));
> }
>
>+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
>+static inline bool pte_uffd_wp(pte_t pte)
>+{
>+	return !!(pte_val(pte) & _PAGE_UFFD_WP);
>+}
>+
>+static inline pte_t pte_mkuffd_wp(pte_t pte)
>+{
>+	return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP));
>+}
>+
>+static inline pte_t pte_clear_uffd_wp(pte_t pte)
>+{
>+	return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP));
>+}
>+
>+static inline bool pte_swp_uffd_wp(pte_t pte)
>+{
>+	return !!(pte_val(pte) & _PAGE_SWP_UFFD_WP);
>+}
>+
>+static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
>+{
>+	return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP);
>+}
>+
>+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
>+{
>+	return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP));
>+}
>+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
>+
> /* static inline pte_t pte_mkread(pte_t pte) */
>
> static inline pte_t pte_mkwrite_novma(pte_t pte)
>@@ -853,6 +885,38 @@ static inline pud_t pud_mkspecial(pud_t pud)
> }
> #endif
>
>+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
>+static inline bool pmd_uffd_wp(pmd_t pmd)
>+{
>+	return pte_uffd_wp(pmd_pte(pmd));
>+}
>+
>+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)));
>+}
>+
>+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)));
>+}
>+
>+static inline bool pmd_swp_uffd_wp(pmd_t pmd)
>+{
>+	return pte_swp_uffd_wp(pmd_pte(pmd));
>+}
>+
>+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)));
>+}
>+
>+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd)
>+{
>+	return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)));
>+}
>+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
>+
> #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> static inline bool pmd_soft_dirty(pmd_t pmd)
> {
>@@ -978,6 +1042,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>  *	bit            0:	_PAGE_PRESENT (zero)
>  *	bit       1 to 2:	(zero)
>  *	bit            3:	_PAGE_SWP_SOFT_DIRTY
>+ *	bit            4:	_PAGE_SWP_UFFD_WP
>  *	bit            5:	_PAGE_PROT_NONE (zero)
>  *	bit            6:	exclusive marker
>  *	bits      7 to 11:	swap type
>-- 
>2.34.1
>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv