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[97.120.250.80]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3158a226f7asm811267a91.10.2025.06.18.18.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 18:50:50 -0700 (PDT) Date: Wed, 18 Jun 2025 18:50:48 -0700 From: Drew Fustini To: Michal Wilczynski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Ulf Hansson Cc: Guo Ren , Fu Wei , Bartosz Golaszewski , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v5 2/8] dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen Message-ID: References: <20250618-apr_14_for_sending-v5-0-27ed33ea5c6f@samsung.com> <20250618-apr_14_for_sending-v5-2-27ed33ea5c6f@samsung.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250618-apr_14_for_sending-v5-2-27ed33ea5c6f@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250618_185051_630297_61AEB2C9 X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Jun 18, 2025 at 12:22:08PM +0200, Michal Wilczynski wrote: > Extend the TH1520 AON to describe the GPU clkgen reset line, required > for proper GPU clock and reset sequencing. > > The T-HEAD TH1520 GPU requires coordinated management of two clocks > (core and sys) and two resets (GPU core reset and GPU clkgen reset). > Only the clkgen reset is exposed at the AON level, to support SoC > specific initialization handled through a dedicated auxiliary power > sequencing driver. The GPU core reset remains described in the GPU > device node, as from the GPU driver's perspective, there is only a > single reset line [1]. > > This follows upstream maintainers' recommendations [2] to abstract SoC > specific details into the PM domain layer rather than exposing them to > drivers directly. > > Link: https://lore.kernel.org/all/816db99d-7088-4c1a-af03-b9a825ac09dc@imgtec.com/ - [1] > Link: https://lore.kernel.org/all/38d9650fc11a674c8b689d6bab937acf@kernel.org/ - [2] > > Reviewed-by: Ulf Hansson > Signed-off-by: Michal Wilczynski > --- > Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml > index bbc183200400de7aadbb21fea21911f6f4227b09..3365124c7fd4736922717bd31caa13272f4a4ea6 100644 > --- a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml > +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml > @@ -32,6 +32,13 @@ properties: > items: > - const: aon > > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: gpu-clkgen > + > "#power-domain-cells": > const: 1 > > > -- > 2.34.1 > Reviewed-by: Drew Fustini I'm wondering what tree this should go through. Ulf took the original patch that created the binding. Thanks, Drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv