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Fri, 20 Jun 2025 09:20:52 -0700 (PDT) Received: from localhost ([216.228.127.128]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7490a6c203bsm2386636b3a.171.2025.06.20.09.20.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jun 2025 09:20:51 -0700 (PDT) Date: Fri, 20 Jun 2025 12:20:47 -0400 From: Yury Norov To: cp0613@linux.alibaba.com Cc: linux@rasmusvillemoes.dk, arnd@arndb.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] bitops: rotate: Add riscv implementation using Zbb extension Message-ID: References: <20250620111610.52750-1-cp0613@linux.alibaba.com> <20250620111610.52750-3-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250620111610.52750-3-cp0613@linux.alibaba.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250620_092054_088161_A6140BA3 X-CRM114-Status: GOOD ( 17.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jun 20, 2025 at 07:16:10PM +0800, cp0613@linux.alibaba.com wrote: > From: Chen Pei > > The RISC-V Zbb extension[1] defines bitwise rotation instructions, > which can be used to implement rotate related functions. > > [1] https://github.com/riscv/riscv-bitmanip/ > > Signed-off-by: Chen Pei > --- > arch/riscv/include/asm/bitops.h | 172 ++++++++++++++++++++++++++++++++ > 1 file changed, 172 insertions(+) > > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > index d59310f74c2b..be247ef9e686 100644 > --- a/arch/riscv/include/asm/bitops.h > +++ b/arch/riscv/include/asm/bitops.h > @@ -20,17 +20,20 @@ > #include > #include > #include > +#include > > #else > #define __HAVE_ARCH___FFS > #define __HAVE_ARCH___FLS > #define __HAVE_ARCH_FFS > #define __HAVE_ARCH_FLS > +#define __HAVE_ARCH_ROTATE > > #include > #include > #include > #include > +#include > > #include > #include > @@ -175,6 +178,175 @@ static __always_inline int variable_fls(unsigned int x) > variable_fls(x_); \ > }) ... > +static inline u8 variable_ror8(u8 word, unsigned int shift) > +{ > + u32 word32 = ((u32)word << 24) | ((u32)word << 16) | ((u32)word << 8) | word; Can you add a comment about what is happening here? Are you sure it's optimized out in case of the 'legacy' alternative? > + > + asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > + RISCV_ISA_EXT_ZBB, 1) > + : : : : legacy); > + > + asm volatile( > + ".option push\n" > + ".option arch,+zbb\n" > + "rorw %0, %1, %2\n" > + ".option pop\n" > + : "=r" (word32) : "r" (word32), "r" (shift) :); > + > + return (u8)word32; > + > +legacy: > + return generic_ror8(word, shift); > +} > + > +#define rol64(word, shift) variable_rol64(word, shift) > +#define ror64(word, shift) variable_ror64(word, shift) > +#define rol32(word, shift) variable_rol32(word, shift) > +#define ror32(word, shift) variable_ror32(word, shift) > +#define rol16(word, shift) variable_rol16(word, shift) > +#define ror16(word, shift) variable_ror16(word, shift) > +#define rol8(word, shift) variable_rol8(word, shift) > +#define ror8(word, shift) variable_ror8(word, shift) Here you wire ror/rol() to the variable_ror/rol() unconditionally, and that breaks compile-time rotation if the parameter is known at compile time. I believe, generic implementation will allow compiler to handle this case better. Can you do a similar thing to what fls() does in the same file? Thanks, Yury > + > #endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) */ > > #include > -- > 2.49.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv