From: Yao Zi <ziyao@disroot.org>
To: Ze Huang <huangze@whut.edu.cn>, Ze Huang <huang.ze@linux.dev>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@gentoo.org>,
Thinh Nguyen <Thinh.Nguyen@synopsys.com>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v7 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1
Date: Tue, 29 Jul 2025 09:44:37 +0000 [thread overview]
Message-ID: <aIiYBaEMNWg20f8-@pie> (raw)
In-Reply-To: <aIhi9JKZvuYh2Rz_@cse-cd03-lnx.ap.qualcomm.com>
On Tue, Jul 29, 2025 at 01:58:12PM +0800, Ze Huang wrote:
> On Tue, Jul 29, 2025 at 01:41:01AM +0000, Yao Zi wrote:
> > On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote:
> > > Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> > > in the SpacemiT K1 SoC. The controller is based on the Synopsys
> > > DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> > > DRD mode.
> > >
> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > > Signed-off-by: Ze Huang <huang.ze@linux.dev>
> > > ---
> > > .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 124 +++++++++++++++++++++
> > > 1 file changed, 124 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > new file mode 100644
> > > index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > @@ -0,0 +1,124 @@
> >
> > ...
> >
> > > + resets:
> > > + items:
> > > + - description: USB3.0 AHB reset
> > > + - description: USB3.0 VCC reset
> > > + - description: USB3.0 PHY reset
> > > + - description: PCIE0 global reset (for combo phy)
> >
> > Why should the USB driver takes care of the PCIe stuff? This sounds
> > strange to me.
> >
>
> On K1, PHY depends on the clocks and resets it shares with the controller,
> and the controller driver is guarantees that any needed clocks are enabled,
> and any resets that affect the PHY are de-asserted before using the PHY.
So does the "PCIe0 global reset" make effects to both USB3 and PCIe
**controllers**? If not, this is something wrong in the devicetree side.
> RESET_PCIE0_GLOBAL reset is necessary during, and only, the calibration stage
> of combo phy.
If it's only used by PHY, why couldn't it be a property of the PHY?
Sorry, but I still cannot get the point.
Regards,
Yao Zi
> To simplify both the driver architecture and the device tree files,
> RESET_PCIE0_GLOBAL (and some other clk/reset) are now managed by the
> relevant controller driver (either USB3 or PCIe0) instead of PHY driver.
>
> Only one of USB3.0 SuperSpeed and PCIe-0 will be activated in a boot.
> PCIe-0 will not be affected when it's working.
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next prev parent reply other threads:[~2025-07-29 9:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-28 16:33 [PATCH v7 0/2] Add SpacemiT K1 USB3.0 host controller support Ze Huang
2025-07-28 16:33 ` [PATCH v7 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1 Ze Huang
2025-07-29 1:41 ` Yao Zi
2025-07-29 5:58 ` Ze Huang
2025-07-29 6:18 ` Krzysztof Kozlowski
2025-07-29 9:44 ` Yao Zi [this message]
2025-07-28 16:33 ` [PATCH v7 2/2] usb: dwc3: add generic driver to support flattened Ze Huang
2025-08-06 0:26 ` Thinh Nguyen
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