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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Aug 16, 2025 at 05:11:09PM +0800, Icenowy Zheng wrote: > This patchset is my changes to the TH1520 clock driver, mainly for > supporting the display controller. > > The first patch is previously a dependency of this patchset before v3, > but a rebase operation in v3 changed it and it's now pulled into this > patchset. > > The 2nd and 3rd ones are functionality additions, with the first one > adding support for enabling/disabling PLLs (for DPU PLL) and the second > one adding support for changing DPU dividers. > > The 4th one is to address hang issues met when testing the DPU driver > w/o clk_ignore_unused command line option. > > The patchset is rebased atop the padctrl0 parent fix patchset (which > contains refactor of ccu_gate) at [1] in v3. > > [1] https://lore.kernel.org/linux-riscv/20250816084445.2582692-1-uwu@icenowy.me/ > > Icenowy Zheng (3): > clk: thead: add support for enabling/disabling PLLs > clk: thead: support changing DPU pixel clock rate > clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL > > Michal Wilczynski (1): > clk: thead: Correct parent for DPU pixel clocks > > drivers/clk/thead/clk-th1520-ap.c | 153 +++++++++++++++++++++++------- > 1 file changed, 121 insertions(+), 32 deletions(-) > > -- > 2.50.1 > Thank you, I've applied this to thead-clk-for-next [1]: c567bc5fc68c clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL 8fede7ff692c clk: thead: support changing DPU pixel clock rate 56a48c1833aa clk: thead: add support for enabling/disabling PLLs c51a37ffea38 clk: thead: Correct parent for DPU pixel clocks -Drew [1] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=thead-clk-for-next _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv