From: Sunil V L <sunilvl@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Rafael J . Wysocki" <rafael@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alexandre Ghiti <alex@ghiti.fr>, Len Brown <lenb@kernel.org>,
Atish Patra <atish.patra@linux.dev>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Troy Mitchell <troy.mitchell@linux.dev>
Subject: Re: [PATCH v2 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling
Date: Tue, 19 Aug 2025 09:55:05 +0530 [thread overview]
Message-ID: <aKP8oeKDwXGMmonO@sunil-laptop> (raw)
In-Reply-To: <20250818143600.894385-2-apatel@ventanamicro.com>
On Mon, Aug 18, 2025 at 08:05:59PM +0530, Anup Patel wrote:
> The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error
> code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must
> not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.
>
> Fixes: 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Troy Mitchell <troy.mitchell@linux.dev>
> ---
> drivers/acpi/riscv/cppc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
> index 440cf9fb91aa..42c1a9052470 100644
> --- a/drivers/acpi/riscv/cppc.c
> +++ b/drivers/acpi/riscv/cppc.c
> @@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
>
> *val = data.ret.value;
>
> - return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
> + return data.ret.error;
> }
>
> return -EINVAL;
> @@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
>
> smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
>
> - return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
> + return data.ret.error;
> }
>
> return -EINVAL;
> --
> 2.43.0
>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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next prev parent reply other threads:[~2025-08-19 4:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 14:35 [PATCH v2 0/2] Common csr_read_num() and csr_write_num() for RISC-V Anup Patel
2025-08-18 14:35 ` [PATCH v2 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling Anup Patel
2025-08-18 19:26 ` Atish Patra
2025-08-19 4:02 ` Nutty.Liu
2025-08-19 4:25 ` Sunil V L [this message]
2025-08-20 7:12 ` Alexandre Ghiti
2025-08-18 14:36 ` [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions Anup Patel
2025-08-18 14:56 ` Andrew Jones
2025-08-18 19:29 ` Atish Patra
2025-08-19 3:26 ` Yao Zi
2025-08-19 3:30 ` Anup Patel
2025-08-19 4:13 ` Yao Zi
2025-08-19 11:01 ` Anup Patel
2025-08-19 4:04 ` Nutty.Liu
2025-09-17 2:40 ` [PATCH v2 0/2] Common csr_read_num() and csr_write_num() for RISC-V patchwork-bot+linux-riscv
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