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Fri, 19 Sep 2025 04:06:21 -0700 (PDT) Received: from andrea ([176.201.192.207]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46138694957sm139550595e9.4.2025.09.19.04.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Sep 2025 04:06:21 -0700 (PDT) Date: Fri, 19 Sep 2025 13:06:15 +0200 From: Andrea Parri To: Xu Lu Cc: corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com, ajones@ventanamicro.com, brs@rivosinc.com, anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [External] Re: [PATCH v3 0/8] riscv: Add Zalasr ISA extension support Message-ID: References: <20250919073714.83063-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250919_040624_284955_6D9E7D59 X-CRM114-Status: GOOD ( 16.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > > > (not a review, just looking at this diff stat) is changing the fastpath > > > > > > read_unlock() > > > read_lock() > > > > > > from something like > > > > > > fence rw,w > > > amodadd.w > > > amoadd.w > > > fence r,rw > > > > > > to > > > > > > fence rw,rw > > > amoadd.w > > > amoadd.w > > > fence rw,rw > > > > > > no matter Zalasr or !Zalasr. Similarly for other atomic operations with > > > release or acquire semantics. I guess the change was not intentional? > > > If it was intentional, it should be properly mentioned in the changelog. > > > > Sorry about that. It is intended. The atomic operation before > > __atomic_acquire_fence or operation after __atomic_release_fence can > > be just a single ld or sd instruction instead of amocas or amoswap. In > > such cases, when the store release operation becomes 'sd.rl', the > > __atomic_acquire_fence via 'fence r, rw' can not ensure FENCE.TSO > > anymore. Thus I replace it with 'fence rw, rw'. But you could apply similar changes you performed for xchg & cmpxchg: use .AQ and .RL for other atomic RMW operations as well, no? AFAICS, that is what arm64 actually does in arch/arm64/include/asm/atomic_{ll_sc,lse}.h . Andrea > This is also the common implementation on other architectures who use > aq/rl instructions like ARM. And you certainly already knew it~ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv