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Thu, 18 Sep 2025 14:24:50 -0700 (PDT) Received: from andrea ([176.201.192.207]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4613e849a41sm96925155e9.20.2025.09.18.14.24.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Sep 2025 14:24:50 -0700 (PDT) Date: Thu, 18 Sep 2025 23:24:41 +0200 From: Andrea Parri To: Guo Ren Cc: Xu Lu , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, ajones@ventanamicro.com, brs@rivosinc.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com Subject: Re: [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Message-ID: References: <20250902042432.78960-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250918_142453_379043_EC29DACB X-CRM114-Status: GOOD ( 11.44 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org [merging replies] > > I prefer option c) at first, it has fewer modification and influence. > Another reason is that store-release-to-load-acquire would give out a > FENCE rw, rw according to RVWMO PPO 7th rule instead of FENCE.TSO, which > is stricter than the Linux requirement you've mentioned. I mean, if "fewer modification" and "not-a-full-fence" were the only arguments, we would probably just stick with the current scheme (b), right? What other arguments are available? Don't get me wrong: no a priori objection from my end; I was really just wondering about the various interests/rationales in the RISC-V kernel community. (It may surprise you, but some communities did consider that "UNLOCK+LOCK is not a full memory barrier" a disadvantage, because briefly "locking should provide strong ordering guarantees and be easy to reason about"; in fact, not just "locking" if we consider x86 or arm64...) > > asm volatile(ALTERNATIVE("fence rw, w;\t\nsb %0, 0(%1)\t\n", \ > > - SB_RL(%0, %1) "\t\nnop\t\n", \ > > + SB_RL(%0, %1) "\t\n fence.tso;\t\n", \ > > 0, RISCV_ISA_EXT_ZALASR, 1) \ > > : : "r" (v), "r" (p) : "memory"); \ nit: Why placing the fence after the store? I imagine that FENCE.TSO could precede the store, this way, the store would actually not need to have that .RL annotation. More importantly, That for (part of) smp_store_release(). Let me stress that my option (c) was meant to include similar changes for _every releases (that is, cmpxchg_release(), atomic_inc_return_release(), and many other), even if most of such releases do not currently create "problematic pairs" with a corresponding acquire: the concern is that future changes in the RISC-V atomics implementation or in generic locking code will introduce pairs of the form FENCE RW,W + .AQ or .RL + FENCE R,RW without anyone noticing... In other words, I was suggesting that RISC-V _continues to meet the ordering property under discussion "by design" rather than "by Andrea or whoever's code auditing/review" (assuming it's feasible, i.e. that it doesn't clash with other people's arguments?); options (a) and (b) were also "designed" following this same criterion. Andrea _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv