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Wysocki" , linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Subject: Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices Message-ID: References: <20250820152316.1012757-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Oct 12, 2025 at 02:07:34AM -0400, Guo Ren wrote: > On Wed, Aug 20, 2025 at 08:53:16PM +0530, Anup Patel wrote: > > The pgprot_dmacoherent() is used when allocating memory for > > non-coherent devices and by default pgprot_dmacoherent() is > > same as pgprot_noncached() unless architecture overrides it. > > > > Currently, there is no pgprot_dmacoherent() definition for > > RISC-V hence non-coherent device memory is being mapped as > > IO thereby making CPU access to such memory slow. > > > > Define pgprot_dmacoherent() to be same as pgprot_writecombine() > > for RISC-V so that CPU access non-coherent device memory as > > NOCACHE which is better than accessing it as IO. > > > > Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") > > Signed-off-by: Anup Patel > > --- > > arch/riscv/include/asm/pgtable.h | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > > index 91697fbf1f90..00d8bdaf1e8d 100644 > > --- a/arch/riscv/include/asm/pgtable.h > > +++ b/arch/riscv/include/asm/pgtable.h > > @@ -653,6 +653,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) > > return __pgprot(prot); > > } > > > > +#define pgprot_dmacoherent pgprot_writecombine > I missed this patch and sent out a duplicate one [1]. Maybe the comments > from [1] could be appended to this one. [1]: https://lore.kernel.org/linux-riscv/20251011155746.1558731-1-guoren@kernel.org/ > > Tested-by: Guo Ren (Alibaba DAMO Academy) > > > + > > /* > > * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By > > * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in > > -- > > 2.43.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv