[PATCH v6 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support

Randolph Lin
2025-10-03T03:38:56Z

Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Only one example is required in the DTS bindings YAML file.

Signed-off-by: Randolph Lin <randolph@andestech.com>
---
.../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml

diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
new file mode 100644
index 000000000000..419468430e7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes QiLai PCIe host controller
+
+description:
+ Andes QiLai PCIe host controller is based on the Synopsys DesignWare
+ PCI core. It shares common features with the PCIe DesignWare core and
+ inherits common properties defined in
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
+
+maintainers:
+ - Randolph Lin <randolph@andestech.com>
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: andestech,qilai-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: APB registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: apb
+ - const: config
+
+ ranges:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map: true
+
+required:
+ - reg
+ - reg-names
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-names
+ - interrupt-map-mask
+ - interrupt-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ bus@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x0 0x80000000 0x0 0x20000000>,
+ <0x0 0x04000000 0x0 0x00001000>,
+ <0x0 0x00000000 0x0 0x00010000>;
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };