Re: [PATCH 0/7] Implement CPU frequency scaling for TH1520

Drew Fustini
2025-12-19T19:32:47Z

On Thu, Nov 20, 2025 at 01:14:09PM +0000, Yao Zi wrote:
> On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly
> reparented to one of the two PLLs: either to cpu_pll0 indirectly through
> c910_i0_clk, or to cpu_pll1 directly. This series fixes a bug in PLL
> enabling code, supports rate change for PLL, and finally implements
> frequency scaling support for c910_clk.
>
> However, to achieve reliable frequency scaling, CPU voltage must be
> adjusted together with frequency, and AON-firmware-based PMIC support
> for TH1520 SoC is still missing in mainline. Thus PATCH 7 that fills OPP
> table for TH1520 CPU and enables CPUfreq is only for testing purpose,
> not intended for upstream (yet).
>
> Testing is done on Lichee Pi 4A board, only operating points safe
> to be used with the the default PMIC configuration are enabled in
> devicetree. I've confirmed there's a performance gain when running
> coremark and some building work compared to the case without cpufreq.
>
> This series is based on next-20251120, thanks for your time and review.
>
> Yao Zi (7):
> dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
> clk: thead: th1520-ap: Poll for PLL lock and wait for stability
> clk: thead: th1520-ap: Add C910 bus clock
> clk: thead: th1520-ap: Support setting PLL rates
> clk: thead: th1520-ap: Add macro to define multiplexers with flags
> clk: thead: th1520-ap: Support CPU frequency scaling
> [Not For Upstream] riscv: dts: thead: Add CPU clock and OPP table for
> TH1520
>
> arch/riscv/boot/dts/thead/th1520.dtsi | 35 ++
> drivers/clk/thead/clk-th1520-ap.c | 350 +++++++++++++++++-
> .../dt-bindings/clock/thead,th1520-clk-ap.h | 1 +
> 3 files changed, 379 insertions(+), 7 deletions(-)
>
> --
> 2.51.2
>

Applied to thead-clk-for-next, thanks!

[1/7] dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
https://git.kernel.org/fustini/c/5f352125f8a0
[1/7] clk: thead: th1520-ap: Poll for PLL lock and wait for stability
https://git.kernel.org/fustini/c/892abfbed71e
[2/7] clk: thead: th1520-ap: Add C910 bus clock
https://git.kernel.org/fustini/c/b436f8a82aaa
[3/7] clk: thead: th1520-ap: Support setting PLL rates
https://git.kernel.org/fustini/c/238cc6316a88
[5/7] clk: thead: th1520-ap: Add macro to define multiplexers with flags
https://git.kernel.org/fustini/c/5dbee3503771
[6/7] clk: thead: th1520-ap: Support CPU frequency scaling
https://git.kernel.org/fustini/c/30441a56b1d1

-Drew