[PATCH] riscv: fix minor typo in syscall.h comment

From: Austin Kim <austindh.kim@gmail.com>
To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr
Cc: linux-riscv@lists.infradead.org, inux-kernel@vger.kernel.org,
	austindh.kim@gmail.com
Subject: [PATCH] riscv: fix minor typo in syscall.h comment
Date: Mon, 19 Jan 2026 16:14:43 +0900	[thread overview]
Message-ID: <aW3Z4zTBvGJpk7a7@adminpc-PowerEdge-R7525> (raw)

From: Austin Kim <austin.kim@lge.com>

Some developers may be confused because RISC-V does not have
a register named r0. Also, orig_r0 is not available in pt_regs structure,
which is specific to riscv. So we had better fix this minor typo.

Signed-off-by: Austin Kim <austin.kim@lge.com>
---
 arch/riscv/include/asm/syscall.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h
index 34313387f..8067e666a 100644
--- a/arch/riscv/include/asm/syscall.h
+++ b/arch/riscv/include/asm/syscall.h
@@ -20,7 +20,7 @@ extern void * const sys_call_table[];
 extern void * const compat_sys_call_table[];
 
 /*
- * Only the low 32 bits of orig_r0 are meaningful, so we return int.
+ * Only the low 32 bits of orig_a0 are meaningful, so we return int.
  * This importantly ignores the high bits on 64-bit, so comparisons
  * sign-extend the low 32 bits.
  */
-- 
2.34.1


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