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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jan 27, 2026 at 07:03:59PM +0800, Xukai Wang wrote: > = > On 2026/1/23 00:01, Jiayu Du wrote: > > On Thu, Jan 22, 2026 at 07:40:29PM +0800, Xukai Wang wrote: > >> On 2026/1/19 16:18, Jiayu Du wrote: > >>>> + > >>>> +K230_CLK_GATE_FORMAT(hs_hclk_src_gate, > >>>> + K230_HS_HCLK_SRC_GATE, > >>>> + 0x18, 0, 0, 0, > >>>> + &hs_hclk_high_src_rate.clk.hw); > >>> Here, you replaced hs_hclk_high_gate(in v9) with hs_hclk_high_src_rat= e, > >> I'm a bit confused, as I don't recall making these specific changes. > >> Looking at the code below, the only difference between v9 and v10 is > >> within the K230_CLK_GATE_FORMAT(hs_hclk_src_gate, ...) definition, whe= re > >> the second parameter changed from 1 to 0. Everything else appears > >> consistent. Could you clarify which change you were referring to? > >>> but after my board test, I find that when hs_hclk_high_gate is turned > >>> off, the mmc/sd and other high-speed subsystems can not work. So maybe > >>> you should not change the hs_hclk_high_gate to hs_hclk_high_src_rate. > >> Regarding the clock management, I recommend explicitly enabling > >> hs_hclk_high_gateas it will be closed by `close unused clocks`. > > Sorry, you are right. It was me who made the changes locally. And I > > saw your reply to this email[1], which you said According to the vendor= 's > > code, the parent clock of hs_hclk_src is hs_hclk_high_src. > > > > Indeed, the parent clock of hs_hclk_src is hs_hclk_high_src. = > = > > but hs_hclk_high_gate is the gate of hs_hclk_high_src. = > = > No. It seems there is some confusion. The hs_hclk_high_src does not have > a gate. In this code segment of the vendor[1], it states that hs_hclk_high is indeed the downstream gate of hs_hclk_high_src. Once hs_hclk_high is turned off, all the high-speed peripherals such as USB, MMC, and SD will fail. This indicates that in the hardware, the gate bit1 actually controls the overall clock switch of the high speed system. I understand that hs_sd0/1_ahb_gate should be enabled during the SD driver probe, and hs_usb0/1_ahb_gate should be enabled during the USB driver probe, but currently there is NO clear driver to ENABLE hi_hclk_high_gate. = So in your code, I think hs_hclk_high_gate should be the gate of = hs_hclk_high_src_rate. And hs_hclk_high_gate should be the parent of hs_hclk_src_gate. link: https://github.com/kendryte/k230_sdk/blob/main/src/little/linux/arch/= riscv/boot/dts/kendryte/clock_provider.dtsi#L497 [1] > = > The clock tree is as follow: > = > =A0 =A0 =A0 =A0pll0_div4 > =A0 =A0 =A0 =A0 =A0 hs_hclk_high_src_rate > =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_hclk_high_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_hclk_src_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 hs_hclk_src_rate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_sd0_ahb_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_sd1_ahb_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_ssi1_ahb_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_ssi2_ahb_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_usb0_ahb_gate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hs_usb1_ahb_gate > = > > So, what you mean is > > that you will add the CLK_IS_CRITICAL flag to the hs_hclk_high_gate? > No, I don't intend to add CLK_IS_CRITICAL flag. Instead, I recommend you > to explicitly enable the clock by using clk_prepare_enable in your driver. I think there is NO clear driver to ENABLE hi_hclk_high_gate. Regards, Jiayu Du > > > > Link: https://lore.kernel.org/all/159615d3-cc52-43be-bf6d-5fe717ef1cc4@= zohomail.com/ [1] > > > > Regards, > > Jiayu Du > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv