From: Herbert Xu <herbert@gondor.apana.org.au>
To: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
"David S . Miller" <davem@davemloft.net>,
linux-riscv@lists.infradead.org, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org,
Chunyan Zhang <zhang.lyra@gmail.com>,
Eric Biggers <ebiggers@kernel.org>
Subject: Re: [PATCH V2] crypto: aegis128: Add RISC-V vector SIMD implementation
Date: Fri, 6 Feb 2026 18:03:08 +0800 [thread overview]
Message-ID: <aYW8XJk44phI3JSG@gondor.apana.org.au> (raw)
In-Reply-To: <20260126092411.243237-1-zhangchunyan@iscas.ac.cn>
On Mon, Jan 26, 2026 at 05:24:11PM +0800, Chunyan Zhang wrote:
> Add a RISC-V vector-accelerated implementation of aegis128 by
> wiring it into the generic SIMD hooks.
>
> This implementation supports vlen values of 512, 256, and 128.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> V2:
> - Add config dependency of RISCV_ISA_V to fix the issue reported by kernel test robot;
> - Add return value in preload_round_data() and aegis128_round().
>
> V1: https://lore.kernel.org/all/20260121101923.64657-1-zhangchunyan@iscas.ac.cn/
> ---
> crypto/Kconfig | 4 +-
> crypto/Makefile | 4 +
> crypto/aegis-rvv.h | 19 +
> crypto/aegis128-rvv-inner.c | 762 ++++++++++++++++++++++++++++++++++++
> crypto/aegis128-rvv.c | 63 +++
> 5 files changed, 850 insertions(+), 2 deletions(-)
> create mode 100644 crypto/aegis-rvv.h
> create mode 100644 crypto/aegis128-rvv-inner.c
> create mode 100644 crypto/aegis128-rvv.c
In light of the recent move of aes from crypto to lib/crypto,
perhaps the same should be done for aegis?
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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next prev parent reply other threads:[~2026-02-06 10:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-26 9:24 [PATCH V2] crypto: aegis128: Add RISC-V vector SIMD implementation Chunyan Zhang
2026-02-06 10:03 ` Herbert Xu [this message]
2026-02-13 0:13 ` Eric Biggers
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