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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cd90aae418sm84839885a.26.2026.03.09.08.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 08:39:57 -0700 (PDT) Date: Mon, 9 Mar 2026 11:39:55 -0400 From: Brian Masney To: Anirudh Srinivasan Cc: Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, fustini@kernel.org, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com, Krzysztof Kozlowski Subject: Re: [PATCH v8 3/3] clk: tenstorrent: Add Atlantis clock controller driver Message-ID: References: <20260306-atlantis-clocks-v8-0-6c9b14a4aa8e@oss.tenstorrent.com> <20260306-atlantis-clocks-v8-3-6c9b14a4aa8e@oss.tenstorrent.com> MIME-Version: 1.0 In-Reply-To: <20260306-atlantis-clocks-v8-3-6c9b14a4aa8e@oss.tenstorrent.com> User-Agent: Mutt/2.2.14 (2025-02-20) X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 8UI9rjffLVgj42-CAMCoqWFNy72UT7LBj7RHEGBjC_4_1773070798 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260309_084001_953613_36824889 X-CRM114-Status: GOOD ( 11.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Mar 06, 2026 at 11:12:19AM -0600, Anirudh Srinivasan wrote: > Add driver for clock controller in Tenstorrent Atlantis SoC. This version > of the driver covers clocks from RCPU subsystem. > > 5 types of clocks generated by this controller: PLLs (PLLs > with bypass functionality and an additional Gate clk at output), Shared > Gates (Multiple Gate clks that share an enable bit), standard Muxes, > Dividers and Gates. All clocks are implemented using custom clk ops and > use the regmap interface associated with the syscon. All clocks are derived > from a 24 Mhz oscillator. > > The reset controller is also setup as an auxiliary device of the clock > controller. > > Signed-off-by: Anirudh Srinivasan Reviewed-by: Brian Masney _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv