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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89a57a18140sm6725596d6.3.2026.03.09.14.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 14:16:01 -0700 (PDT) Date: Mon, 9 Mar 2026 17:15:58 -0400 From: Brian Masney To: Drew Fustini Cc: Stephen Boyd , Anirudh Srinivasan , Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Philipp Zabel , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com, Krzysztof Kozlowski Subject: Re: [PATCH v8 3/3] clk: tenstorrent: Add Atlantis clock controller driver Message-ID: References: <20260306-atlantis-clocks-v8-0-6c9b14a4aa8e@oss.tenstorrent.com> <20260306-atlantis-clocks-v8-3-6c9b14a4aa8e@oss.tenstorrent.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: sRAfBO9BE_DAop2Tfq8soeZ9tgz2rq9BuvYtelI-AbM_1773090962 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260309_141726_420201_14AD05D9 X-CRM114-Status: GOOD ( 18.34 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Mar 09, 2026 at 01:11:02PM -0700, Drew Fustini wrote: > On Fri, Mar 06, 2026 at 11:12:19AM -0600, Anirudh Srinivasan wrote: > > Add driver for clock controller in Tenstorrent Atlantis SoC. This version > > of the driver covers clocks from RCPU subsystem. > > > > 5 types of clocks generated by this controller: PLLs (PLLs > > with bypass functionality and an additional Gate clk at output), Shared > > Gates (Multiple Gate clks that share an enable bit), standard Muxes, > > Dividers and Gates. All clocks are implemented using custom clk ops and > > use the regmap interface associated with the syscon. All clocks are derived > > from a 24 Mhz oscillator. > > > > The reset controller is also setup as an auxiliary device of the clock > > controller. > > > > Signed-off-by: Anirudh Srinivasan > > --- > > MAINTAINERS | 1 + > > drivers/clk/Kconfig | 1 + > > drivers/clk/Makefile | 1 + > > drivers/clk/tenstorrent/Kconfig | 14 + > > drivers/clk/tenstorrent/Makefile | 3 + > > drivers/clk/tenstorrent/atlantis-prcm.c | 870 ++++++++++++++++++++++++++++++++ > > 6 files changed, 890 insertions(+) > > Hi Stephen, does it make sense for me to create clk branches [1] in the > tenstorrent repo on kernel.org for Atlantis patches to go through? I am not Stephen, but that's the approach that all of the other SoC vendors use for the clk subsystem, so I would say yes. Brian _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv