[PATCH v2 0/9] spi: enable the SpacemiT K1 SoC QSPI

[PATCH v2 0/9] spi: enable the SpacemiT K1 SoC QSPI

[Alex Elder]

This series adds support for the SpacemiT K1 SoC QSPI.  This IP
is generally compatible with the Freescale QSPI driver, requiring
three minor changes to enable it to be supported.  The changes
are:
  - Adding support for optional resets
  - Having the clock *not* be disabled when changing its rate
  - Allowing the size of storage blocks written to flash chips
    to be set to something different from the AHB buffer size

    					-Alex

This series is available here:
  https://github.com/riscstar/linux/tree/outgoing/qspi-v2
  
Version 2 addresses comments recieved during review of v1:
- The "reset" property now only applies to spacemit,k1-qspi compatible.
- Patch 1 (previously patch 2) now points out that this is the first
  non-Freescale device using the binding.
- Added Frank Li's Reviewed-by on patch 3.
- A quirk flag has been renamed to be QUADSPI_QUIRK_SKIP_CLK_DISABLE.
- The predicate for that quirk now returns bool type.
- All other similar predicates now return bool type; this is done in a new
  patch (patch 4).
- If non-zero, new field fsl_qspi_devtype_data->sfa_size defines the
  size of the serial flash regions, rather than ahb_buf_size.
- A continued line in the Kconfig is now aligned.
- Patch descriptions are wrapped at 75 columns.

Alex Elder (9):
  dt-bindings: spi: fsl-qspi: support SpacemiT K1
  dt-bindings: spi: fsl-qspi: add optional resets
  spi: fsl-qspi: add optional reset support
  spi: fsl-qspi: switch predicates to bool
  spi: fsl-qspi: add a clock disable quirk
  spi: fsl-qspi: allot 1KB per chip
  spi: fsl-qspi: support the SpacemiT K1 SoC
  riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3
  riscv: defconfig: enable SPI_FSL_QUADSPI as a module

 .../bindings/spi/fsl,spi-fsl-qspi.yaml        | 16 ++++
 .../boot/dts/spacemit/k1-bananapi-f3.dts      |  6 ++
 arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi  | 21 +++++
 arch/riscv/boot/dts/spacemit/k1.dtsi          | 16 ++++
 arch/riscv/configs/defconfig                  |  1 +
 drivers/spi/Kconfig                           |  3 +-
 drivers/spi/spi-fsl-qspi.c                    | 87 +++++++++++++------
 7 files changed, 124 insertions(+), 26 deletions(-)


base-commit: efb26a23ed5f5dc3554886ab398f559dcb1de96b
-- 
2.43.0


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[PATCH v2 1/9] dt-bindings: spi: fsl-qspi: support SpacemiT K1

[Alex Elder]

Add the SpacemiT K1 SoC QSPI IP to the list of supported hardware.  This
is the first non-Freescale device represented here.  It has a nearly
identidal register set, and this binding correctly describes the hardware.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - Point out that this is the first non-Freescale device used here

 Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
index f2dd20370dbb3..5e6aff1bc2ed3 100644
--- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
@@ -22,6 +22,7 @@ properties:
           - fsl,imx6ul-qspi
           - fsl,ls1021a-qspi
           - fsl,ls2080a-qspi
+          - spacemit,k1-qspi
       - items:
           - enum:
               - fsl,ls1043a-qspi
-- 
2.43.0


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Re: [PATCH v2 1/9] dt-bindings: spi: fsl-qspi: support SpacemiT K1

[Conor Dooley]

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On Thu, Oct 23, 2025 at 12:59:13PM -0500, Alex Elder wrote:
> Add the SpacemiT K1 SoC QSPI IP to the list of supported hardware.  This
> is the first non-Freescale device represented here.  It has a nearly
> identidal register set, and this binding correctly describes the hardware.
> 
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - Point out that this is the first non-Freescale device used here

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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Re: [PATCH v2 1/9] dt-bindings: spi: fsl-qspi: support SpacemiT K1

[Frank Li]

On Thu, Oct 23, 2025 at 12:59:13PM -0500, Alex Elder wrote:
> Add the SpacemiT K1 SoC QSPI IP to the list of supported hardware.  This
> is the first non-Freescale device represented here.  It has a nearly
> identidal register set, and this binding correctly describes the hardware.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> v2: - Point out that this is the first non-Freescale device used here
>
>  Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
> index f2dd20370dbb3..5e6aff1bc2ed3 100644
> --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
> @@ -22,6 +22,7 @@ properties:
>            - fsl,imx6ul-qspi
>            - fsl,ls1021a-qspi
>            - fsl,ls2080a-qspi
> +          - spacemit,k1-qspi
>        - items:
>            - enum:
>                - fsl,ls1043a-qspi
> --
> 2.43.0
>

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[PATCH v2 2/9] dt-bindings: spi: fsl-qspi: add optional resets

[Alex Elder]

Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - The "reset" property now only applies to spacemit,k1-qspi compatible

 .../devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
index 5e6aff1bc2ed3..edd3158a6f2e8 100644
--- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
@@ -55,6 +55,21 @@ properties:
       - const: qspi_en
       - const: qspi
 
+  resets:
+    items:
+      - description: SoC QSPI reset
+      - description: SoC QSPI bus reset
+
+if:
+  properties:
+    compatible:
+      not:
+        contains:
+          const: spacemit,k1-qspi
+then:
+  properties:
+    resets: false
+
 required:
   - compatible
   - reg
-- 
2.43.0


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Re: [PATCH v2 2/9] dt-bindings: spi: fsl-qspi: add optional resets

[Conor Dooley]

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On Thu, Oct 23, 2025 at 12:59:14PM -0500, Alex Elder wrote:
> Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP.
> 
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - The "reset" property now only applies to spacemit,k1-qspi compatible

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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Re: [PATCH v2 2/9] dt-bindings: spi: fsl-qspi: add optional resets

[Frank Li]

On Thu, Oct 23, 2025 at 12:59:14PM -0500, Alex Elder wrote:
> Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - The "reset" property now only applies to spacemit,k1-qspi compatible
>
>  .../devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
> index 5e6aff1bc2ed3..edd3158a6f2e8 100644
> --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
> @@ -55,6 +55,21 @@ properties:
>        - const: qspi_en
>        - const: qspi
>
> +  resets:
> +    items:
> +      - description: SoC QSPI reset
> +      - description: SoC QSPI bus reset
> +
> +if:
> +  properties:
> +    compatible:
> +      not:
> +        contains:
> +          const: spacemit,k1-qspi
> +then:
> +  properties:
> +    resets: false
> +

strange, if-then should be under allOf, I have not seen you add allOf. And
original file have not allOf.

Frank

>  required:
>    - compatible
>    - reg
> --
> 2.43.0
>

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Re: [PATCH v2 2/9] dt-bindings: spi: fsl-qspi: add optional resets

[Alex Elder]

On 10/23/25 6:32 PM, Frank Li wrote:
> On Thu, Oct 23, 2025 at 12:59:14PM -0500, Alex Elder wrote:
>> Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP.
>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> v2: - The "reset" property now only applies to spacemit,k1-qspi compatible
>>
>>   .../devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
>> index 5e6aff1bc2ed3..edd3158a6f2e8 100644
>> --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
>> @@ -55,6 +55,21 @@ properties:
>>         - const: qspi_en
>>         - const: qspi
>>
>> +  resets:
>> +    items:
>> +      - description: SoC QSPI reset
>> +      - description: SoC QSPI bus reset
>> +
>> +if:
>> +  properties:
>> +    compatible:
>> +      not:
>> +        contains:
>> +          const: spacemit,k1-qspi
>> +then:
>> +  properties:
>> +    resets: false
>> +
> 
> strange, if-then should be under allOf, I have not seen you add allOf. And
> original file have not allOf.

The file currently has allOf at the top, to reference
spi-controller.yaml.  I'll include this next time within
that allOf.

					-Alex

> 
> Frank
> 
>>   required:
>>     - compatible
>>     - reg
>> --
>> 2.43.0
>>


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[PATCH v2 3/9] spi: fsl-qspi: add optional reset support

[Alex Elder]

Add support for one or more optional exclusive resets.  These simply need
to be deasserted at probe time, and can remain that way for the life of the
device.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - Added Frank Li's Reviewed-by

 drivers/spi/spi-fsl-qspi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index c887abb028d77..1e27647dd2a09 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -36,6 +36,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_qos.h>
+#include <linux/reset.h>
 #include <linux/sizes.h>
 
 #include <linux/spi/spi.h>
@@ -267,6 +268,7 @@ struct fsl_qspi {
 	const struct fsl_qspi_devtype_data *devtype_data;
 	struct mutex lock;
 	struct completion c;
+	struct reset_control *resets;
 	struct clk *clk, *clk_en;
 	struct pm_qos_request pm_qos_req;
 	struct device *dev;
@@ -857,6 +859,8 @@ static void fsl_qspi_cleanup(void *data)
 {
 	struct fsl_qspi *q = data;
 
+	reset_control_assert(q->resets);
+
 	fsl_qspi_clk_disable_unprep(q);
 
 	mutex_destroy(&q->lock);
@@ -902,6 +906,10 @@ static int fsl_qspi_probe(struct platform_device *pdev)
 	if (!q->ahb_addr)
 		return -ENOMEM;
 
+	q->resets = devm_reset_control_array_get_optional_exclusive(dev);
+	if (IS_ERR(q->resets))
+		return PTR_ERR(q->resets);
+
 	/* find the clocks */
 	q->clk_en = devm_clk_get(dev, "qspi_en");
 	if (IS_ERR(q->clk_en))
@@ -923,6 +931,10 @@ static int fsl_qspi_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	ret = reset_control_deassert(q->resets);
+	if (ret)
+		return ret;
+
 	/* find the irq */
 	ret = platform_get_irq(pdev, 0);
 	if (ret < 0)
-- 
2.43.0


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[PATCH v2 4/9] spi: fsl-qspi: switch predicates to bool

[Alex Elder]

Change all the needs_*() functions so they are no longer inline, and return
bool rather than int.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - New patch: predicates now return bool type and drop inline

  patch (patch 4).
 drivers/spi/spi-fsl-qspi.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index 1e27647dd2a09..1944e63169d36 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -276,34 +276,34 @@ struct fsl_qspi {
 	u32 memmap_phy;
 };
 
-static inline int needs_swap_endian(struct fsl_qspi *q)
+static bool needs_swap_endian(struct fsl_qspi *q)
 {
-	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
+	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN);
 }
 
-static inline int needs_4x_clock(struct fsl_qspi *q)
+static bool needs_4x_clock(struct fsl_qspi *q)
 {
-	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
+	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK);
 }
 
-static inline int needs_fill_txfifo(struct fsl_qspi *q)
+static bool needs_fill_txfifo(struct fsl_qspi *q)
 {
-	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
+	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890);
 }
 
-static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
+static bool needs_wakeup_wait_mode(struct fsl_qspi *q)
 {
-	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
+	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618);
 }
 
-static inline int needs_amba_base_offset(struct fsl_qspi *q)
+static bool needs_amba_base_offset(struct fsl_qspi *q)
 {
 	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
 }
 
-static inline int needs_tdh_setting(struct fsl_qspi *q)
+static bool needs_tdh_setting(struct fsl_qspi *q)
 {
-	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
+	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
 }
 
 /*
-- 
2.43.0


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Re: [PATCH v2 4/9] spi: fsl-qspi: switch predicates to bool

[Frank Li]

On Thu, Oct 23, 2025 at 12:59:16PM -0500, Alex Elder wrote:
> Change all the needs_*() functions so they are no longer inline, and return
> bool rather than int.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - New patch: predicates now return bool type and drop inline
>
>   patch (patch 4).
>  drivers/spi/spi-fsl-qspi.c | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index 1e27647dd2a09..1944e63169d36 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -276,34 +276,34 @@ struct fsl_qspi {
>  	u32 memmap_phy;
>  };
>
> -static inline int needs_swap_endian(struct fsl_qspi *q)
> +static bool needs_swap_endian(struct fsl_qspi *q)

why drop inline, and next patch needs_disable_clk() have inline.

Frank
>  {
> -	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN);
>  }
>
> -static inline int needs_4x_clock(struct fsl_qspi *q)
> +static bool needs_4x_clock(struct fsl_qspi *q)
>  {
> -	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK);
>  }
>
> -static inline int needs_fill_txfifo(struct fsl_qspi *q)
> +static bool needs_fill_txfifo(struct fsl_qspi *q)
>  {
> -	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890);
>  }
>
> -static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
> +static bool needs_wakeup_wait_mode(struct fsl_qspi *q)
>  {
> -	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618);
>  }
>
> -static inline int needs_amba_base_offset(struct fsl_qspi *q)
> +static bool needs_amba_base_offset(struct fsl_qspi *q)
>  {
>  	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
>  }
>
> -static inline int needs_tdh_setting(struct fsl_qspi *q)
> +static bool needs_tdh_setting(struct fsl_qspi *q)
>  {
> -	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
>  }
>
>  /*
> --
> 2.43.0
>

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Re: [PATCH v2 4/9] spi: fsl-qspi: switch predicates to bool

[Alex Elder]

On 10/23/25 6:33 PM, Frank Li wrote:
> On Thu, Oct 23, 2025 at 12:59:16PM -0500, Alex Elder wrote:
>> Change all the needs_*() functions so they are no longer inline, and return
>> bool rather than int.
>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> v2: - New patch: predicates now return bool type and drop inline
>>
>>    patch (patch 4).
>>   drivers/spi/spi-fsl-qspi.c | 22 +++++++++++-----------
>>   1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
>> index 1e27647dd2a09..1944e63169d36 100644
>> --- a/drivers/spi/spi-fsl-qspi.c
>> +++ b/drivers/spi/spi-fsl-qspi.c
>> @@ -276,34 +276,34 @@ struct fsl_qspi {
>>   	u32 memmap_phy;
>>   };
>>
>> -static inline int needs_swap_endian(struct fsl_qspi *q)
>> +static bool needs_swap_endian(struct fsl_qspi *q)
> 
> why drop inline, and next patch needs_disable_clk() have inline.

That was a mistake.  I intend to drop inline on all of them.
Will fix.

					-Alex

> 
> Frank
>>   {
>> -	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;
>> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN);
>>   }
>>
>> -static inline int needs_4x_clock(struct fsl_qspi *q)
>> +static bool needs_4x_clock(struct fsl_qspi *q)
>>   {
>> -	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;
>> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK);
>>   }
>>
>> -static inline int needs_fill_txfifo(struct fsl_qspi *q)
>> +static bool needs_fill_txfifo(struct fsl_qspi *q)
>>   {
>> -	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;
>> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890);
>>   }
>>
>> -static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
>> +static bool needs_wakeup_wait_mode(struct fsl_qspi *q)
>>   {
>> -	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
>> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618);
>>   }
>>
>> -static inline int needs_amba_base_offset(struct fsl_qspi *q)
>> +static bool needs_amba_base_offset(struct fsl_qspi *q)
>>   {
>>   	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
>>   }
>>
>> -static inline int needs_tdh_setting(struct fsl_qspi *q)
>> +static bool needs_tdh_setting(struct fsl_qspi *q)
>>   {
>> -	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
>> +	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
>>   }
>>
>>   /*
>> --
>> 2.43.0
>>


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[PATCH v2 5/9] spi: fsl-qspi: add a clock disable quirk

[Alex Elder]

The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the
clock when changing its rate.  Add a new quirk to indicate that disabling
and enabling the clock should be skipped when changing its rate for
operations.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - The quirk flag is now named QUADSPI_QUIRK_SKIP_CLK_DISABLE
    - The predicate now returns bool and is not inline

 drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index 1944e63169d36..c21e3804cb032 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -197,6 +197,11 @@
  */
 #define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)
 
+/*
+ * Do not disable the "qspi" clock when changing its rate.
+ */
+#define QUADSPI_QUIRK_SKIP_CLK_DISABLE	BIT(6)
+
 struct fsl_qspi_devtype_data {
 	unsigned int rxfifo;
 	unsigned int txfifo;
@@ -306,6 +311,11 @@ static bool needs_tdh_setting(struct fsl_qspi *q)
 	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
 }
 
+static inline bool needs_clk_disable(struct fsl_qspi *q)
+{
+	return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
+}
+
 /*
  * An IC bug makes it necessary to rearrange the 32-bit data.
  * Later chips, such as IMX6SLX, have fixed this bug.
@@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
 	if (needs_4x_clock(q))
 		rate *= 4;
 
-	fsl_qspi_clk_disable_unprep(q);
+	if (needs_clk_disable(q))
+		fsl_qspi_clk_disable_unprep(q);
 
 	ret = clk_set_rate(q->clk, rate);
 	if (ret)
 		return;
 
-	ret = fsl_qspi_clk_prep_enable(q);
-	if (ret)
-		return;
+	if (needs_clk_disable(q)) {
+		ret = fsl_qspi_clk_prep_enable(q);
+		if (ret)
+			return;
+	}
 
 	q->selected = spi_get_chipselect(spi, 0);
 
-- 
2.43.0


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Re: [PATCH v2 5/9] spi: fsl-qspi: add a clock disable quirk

[Frank Li]

On Thu, Oct 23, 2025 at 12:59:17PM -0500, Alex Elder wrote:
> The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the
> clock when changing its rate.  Add a new quirk to indicate that disabling
> and enabling the clock should be skipped when changing its rate for
> operations.

remove "for operations."

>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - The quirk flag is now named QUADSPI_QUIRK_SKIP_CLK_DISABLE
>     - The predicate now returns bool and is not inline
>
>  drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
>  1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index 1944e63169d36..c21e3804cb032 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -197,6 +197,11 @@
>   */
>  #define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)
>
> +/*
> + * Do not disable the "qspi" clock when changing its rate.
> + */
> +#define QUADSPI_QUIRK_SKIP_CLK_DISABLE	BIT(6)
> +
>  struct fsl_qspi_devtype_data {
>  	unsigned int rxfifo;
>  	unsigned int txfifo;
> @@ -306,6 +311,11 @@ static bool needs_tdh_setting(struct fsl_qspi *q)
>  	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
>  }
>
> +static inline bool needs_clk_disable(struct fsl_qspi *q)

needs_skip_clk_disable()

Frank
> +{
> +	return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
> +}
> +
>  /*
>   * An IC bug makes it necessary to rearrange the 32-bit data.
>   * Later chips, such as IMX6SLX, have fixed this bug.
> @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
>  	if (needs_4x_clock(q))
>  		rate *= 4;
>
> -	fsl_qspi_clk_disable_unprep(q);
> +	if (needs_clk_disable(q))
> +		fsl_qspi_clk_disable_unprep(q);
>
>  	ret = clk_set_rate(q->clk, rate);
>  	if (ret)
>  		return;
>
> -	ret = fsl_qspi_clk_prep_enable(q);
> -	if (ret)
> -		return;
> +	if (needs_clk_disable(q)) {
> +		ret = fsl_qspi_clk_prep_enable(q);
> +		if (ret)
> +			return;
> +	}
>
>  	q->selected = spi_get_chipselect(spi, 0);
>
> --
> 2.43.0
>

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Re: [PATCH v2 5/9] spi: fsl-qspi: add a clock disable quirk

[Alex Elder]

On 10/23/25 6:36 PM, Frank Li wrote:
> On Thu, Oct 23, 2025 at 12:59:17PM -0500, Alex Elder wrote:
>> The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the
>> clock when changing its rate.  Add a new quirk to indicate that disabling
>> and enabling the clock should be skipped when changing its rate for
>> operations.
> 
> remove "for operations."

OK.

>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> v2: - The quirk flag is now named QUADSPI_QUIRK_SKIP_CLK_DISABLE
>>      - The predicate now returns bool and is not inline
>>
>>   drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
>>   1 file changed, 17 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
>> index 1944e63169d36..c21e3804cb032 100644
>> --- a/drivers/spi/spi-fsl-qspi.c
>> +++ b/drivers/spi/spi-fsl-qspi.c
>> @@ -197,6 +197,11 @@
>>    */
>>   #define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)
>>
>> +/*
>> + * Do not disable the "qspi" clock when changing its rate.
>> + */
>> +#define QUADSPI_QUIRK_SKIP_CLK_DISABLE	BIT(6)
>> +
>>   struct fsl_qspi_devtype_data {
>>   	unsigned int rxfifo;
>>   	unsigned int txfifo;
>> @@ -306,6 +311,11 @@ static bool needs_tdh_setting(struct fsl_qspi *q)
>>   	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
>>   }
>>
>> +static inline bool needs_clk_disable(struct fsl_qspi *q)
> 
> needs_skip_clk_disable()

OK.  I was trying to avoid the double-negative:

     if (!needs_skip_clk_disasble())
	clk_disable...()

But I'll do as you suggest.

Thanks.

					-Alex
> 
> Frank
>> +{
>> +	return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
>> +}
>> +
>>   /*
>>    * An IC bug makes it necessary to rearrange the 32-bit data.
>>    * Later chips, such as IMX6SLX, have fixed this bug.
>> @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
>>   	if (needs_4x_clock(q))
>>   		rate *= 4;
>>
>> -	fsl_qspi_clk_disable_unprep(q);
>> +	if (needs_clk_disable(q))
>> +		fsl_qspi_clk_disable_unprep(q);
>>
>>   	ret = clk_set_rate(q->clk, rate);
>>   	if (ret)
>>   		return;
>>
>> -	ret = fsl_qspi_clk_prep_enable(q);
>> -	if (ret)
>> -		return;
>> +	if (needs_clk_disable(q)) {
>> +		ret = fsl_qspi_clk_prep_enable(q);
>> +		if (ret)
>> +			return;
>> +	}
>>
>>   	q->selected = spi_get_chipselect(spi, 0);
>>
>> --
>> 2.43.0
>>


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Re: [PATCH v2 5/9] spi: fsl-qspi: add a clock disable quirk

[Frank Li]

On Thu, Oct 23, 2025 at 07:04:10PM -0500, Alex Elder wrote:
> On 10/23/25 6:36 PM, Frank Li wrote:
> > On Thu, Oct 23, 2025 at 12:59:17PM -0500, Alex Elder wrote:
> > > The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the
> > > clock when changing its rate.  Add a new quirk to indicate that disabling
> > > and enabling the clock should be skipped when changing its rate for
> > > operations.
> >
> > remove "for operations."
>
> OK.
>
> > >
> > > Signed-off-by: Alex Elder <elder@riscstar.com>
> > > ---
> > > v2: - The quirk flag is now named QUADSPI_QUIRK_SKIP_CLK_DISABLE
> > >      - The predicate now returns bool and is not inline
> > >
> > >   drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++----
> > >   1 file changed, 17 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> > > index 1944e63169d36..c21e3804cb032 100644
> > > --- a/drivers/spi/spi-fsl-qspi.c
> > > +++ b/drivers/spi/spi-fsl-qspi.c
> > > @@ -197,6 +197,11 @@
> > >    */
> > >   #define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)
> > >
> > > +/*
> > > + * Do not disable the "qspi" clock when changing its rate.
> > > + */
> > > +#define QUADSPI_QUIRK_SKIP_CLK_DISABLE	BIT(6)
> > > +
> > >   struct fsl_qspi_devtype_data {
> > >   	unsigned int rxfifo;
> > >   	unsigned int txfifo;
> > > @@ -306,6 +311,11 @@ static bool needs_tdh_setting(struct fsl_qspi *q)
> > >   	return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
> > >   }
> > >
> > > +static inline bool needs_clk_disable(struct fsl_qspi *q)
> >
> > needs_skip_clk_disable()
>
> OK.  I was trying to avoid the double-negative:
>
>     if (!needs_skip_clk_disasble())
> 	clk_disable...()

Oh, Make senso, needs_clk_disable() is fine

Frank

>
> But I'll do as you suggest.
>
> Thanks.
>
> 					-Alex
> >
> > Frank
> > > +{
> > > +	return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
> > > +}
> > > +
> > >   /*
> > >    * An IC bug makes it necessary to rearrange the 32-bit data.
> > >    * Later chips, such as IMX6SLX, have fixed this bug.
> > > @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi,
> > >   	if (needs_4x_clock(q))
> > >   		rate *= 4;
> > >
> > > -	fsl_qspi_clk_disable_unprep(q);
> > > +	if (needs_clk_disable(q))
> > > +		fsl_qspi_clk_disable_unprep(q);
> > >
> > >   	ret = clk_set_rate(q->clk, rate);
> > >   	if (ret)
> > >   		return;
> > >
> > > -	ret = fsl_qspi_clk_prep_enable(q);
> > > -	if (ret)
> > > -		return;
> > > +	if (needs_clk_disable(q)) {
> > > +		ret = fsl_qspi_clk_prep_enable(q);
> > > +		if (ret)
> > > +			return;
> > > +	}
> > >
> > >   	q->selected = spi_get_chipselect(spi, 0);
> > >
> > > --
> > > 2.43.0
> > >
>

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Re: [PATCH v2 5/9] spi: fsl-qspi: add a clock disable quirk

[Alex Elder]

On 10/23/25 9:07 PM, Frank Li wrote:
>>>> +static inline bool needs_clk_disable(struct fsl_qspi *q)
>>> needs_skip_clk_disable()
>> OK.  I was trying to avoid the double-negative:
>>
>>      if (!needs_skip_clk_disasble())
>> 	clk_disable...()
> Oh, Make senso, needs_clk_disable() is fine

I will leave it as it was:  needs_clk_disable().  Thanks.	-Alex

> Frank
> 
>> But I'll do as you suggest.



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[PATCH v2 6/9] spi: fsl-qspi: allot 1KB per chip

[Alex Elder]

In fsl_qspi_default_setup(), four registers define the size of blocks of
data to written to each of four chips that comprise SPI NOR flash storage.
They are currently defined to be the same as the AHB buffer size (which is
always 1KB).

The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these
four sizes to be multiples of 1024 bytes.

Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if
non-zero, will be used instead of the AHB buffer size to define the size of
these chip regions.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - New field fsl_qspi_devtype_data->sfa_size now defines the size of
       the serial flash regions if it's non-zero

 drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index c21e3804cb032..a474d1b341b6a 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data {
 	unsigned int txfifo;
 	int invalid_mstrid;
 	unsigned int ahb_buf_size;
+	unsigned int sfa_size;
 	unsigned int quirks;
 	bool little_endian;
 };
@@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
 {
 	void __iomem *base = q->iobase;
 	u32 reg, addr_offset = 0;
+	u32 size;
 	int ret;
 
 	/* disable and unprepare clock to avoid glitch pass to controller */
@@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
 	 * In HW there can be a maximum of four chips on two buses with
 	 * two chip selects on each bus. We use four chip selects in SW
 	 * to differentiate between the four chips.
-	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
-	 * SFB2AD accordingly.
+	 *
+	 * By default we write the AHB buffer size to each chip, but
+	 * a different size can be specified with devtype_data->sfa_size.
+	 * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the
+	 * top (end) of these four regions.
 	 */
-	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
-		    base + QUADSPI_SFA1AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
-		    base + QUADSPI_SFA2AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
-		    base + QUADSPI_SFB1AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
-		    base + QUADSPI_SFB2AD);
+	size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
+	qspi_writel(q, addr_offset + 1 * size, base + QUADSPI_SFA1AD);
+	qspi_writel(q, addr_offset + 2 * size, base + QUADSPI_SFA2AD);
+	qspi_writel(q, addr_offset + 3 * size, base + QUADSPI_SFB1AD);
+	qspi_writel(q, addr_offset + 4 * size, base + QUADSPI_SFB2AD);
 
 	q->selected = -1;
 
-- 
2.43.0


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Re: [PATCH v2 6/9] spi: fsl-qspi: allot 1KB per chip

[Frank Li]

On Thu, Oct 23, 2025 at 12:59:18PM -0500, Alex Elder wrote:
> In fsl_qspi_default_setup(), four registers define the size of blocks of
> data to written to each of four chips that comprise SPI NOR flash storage.
> They are currently defined to be the same as the AHB buffer size (which is
> always 1KB).
>
> The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these
> four sizes to be multiples of 1024 bytes.
>
> Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if
> non-zero, will be used instead of the AHB buffer size to define the size of
> these chip regions.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - New field fsl_qspi_devtype_data->sfa_size now defines the size of
>        the serial flash regions if it's non-zero
>
>  drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++----------
>  1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index c21e3804cb032..a474d1b341b6a 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data {
>  	unsigned int txfifo;
>  	int invalid_mstrid;
>  	unsigned int ahb_buf_size;
> +	unsigned int sfa_size;
>  	unsigned int quirks;
>  	bool little_endian;
>  };
> @@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
>  {
>  	void __iomem *base = q->iobase;
>  	u32 reg, addr_offset = 0;
> +	u32 size;

I think use 'sfa_size' is better to read code.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  	int ret;
>
>  	/* disable and unprepare clock to avoid glitch pass to controller */
> @@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
>  	 * In HW there can be a maximum of four chips on two buses with
>  	 * two chip selects on each bus. We use four chip selects in SW
>  	 * to differentiate between the four chips.
> -	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
> -	 * SFB2AD accordingly.
> +	 *
> +	 * By default we write the AHB buffer size to each chip, but
> +	 * a different size can be specified with devtype_data->sfa_size.
> +	 * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the
> +	 * top (end) of these four regions.
>  	 */
> -	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
> -		    base + QUADSPI_SFA1AD);
> -	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
> -		    base + QUADSPI_SFA2AD);
> -	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
> -		    base + QUADSPI_SFB1AD);
> -	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
> -		    base + QUADSPI_SFB2AD);
> +	size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
> +	qspi_writel(q, addr_offset + 1 * size, base + QUADSPI_SFA1AD);
> +	qspi_writel(q, addr_offset + 2 * size, base + QUADSPI_SFA2AD);
> +	qspi_writel(q, addr_offset + 3 * size, base + QUADSPI_SFB1AD);
> +	qspi_writel(q, addr_offset + 4 * size, base + QUADSPI_SFB2AD);
>
>  	q->selected = -1;
>
> --
> 2.43.0
>

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Re: [PATCH v2 6/9] spi: fsl-qspi: allot 1KB per chip

[Alex Elder]

On 10/23/25 6:38 PM, Frank Li wrote:
> On Thu, Oct 23, 2025 at 12:59:18PM -0500, Alex Elder wrote:
>> In fsl_qspi_default_setup(), four registers define the size of blocks of
>> data to written to each of four chips that comprise SPI NOR flash storage.
>> They are currently defined to be the same as the AHB buffer size (which is
>> always 1KB).
>>
>> The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these
>> four sizes to be multiples of 1024 bytes.
>>
>> Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if
>> non-zero, will be used instead of the AHB buffer size to define the size of
>> these chip regions.
>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> v2: - New field fsl_qspi_devtype_data->sfa_size now defines the size of
>>         the serial flash regions if it's non-zero
>>
>>   drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++----------
>>   1 file changed, 12 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
>> index c21e3804cb032..a474d1b341b6a 100644
>> --- a/drivers/spi/spi-fsl-qspi.c
>> +++ b/drivers/spi/spi-fsl-qspi.c
>> @@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data {
>>   	unsigned int txfifo;
>>   	int invalid_mstrid;
>>   	unsigned int ahb_buf_size;
>> +	unsigned int sfa_size;
>>   	unsigned int quirks;
>>   	bool little_endian;
>>   };
>> @@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
>>   {
>>   	void __iomem *base = q->iobase;
>>   	u32 reg, addr_offset = 0;
>> +	u32 size;
> 
> I think use 'sfa_size' is better to read code.

OK I'll rename in the next version.  Thanks.	-Alex

> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>>   	int ret;
>>
>>   	/* disable and unprepare clock to avoid glitch pass to controller */
>> @@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
>>   	 * In HW there can be a maximum of four chips on two buses with
>>   	 * two chip selects on each bus. We use four chip selects in SW
>>   	 * to differentiate between the four chips.
>> -	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
>> -	 * SFB2AD accordingly.
>> +	 *
>> +	 * By default we write the AHB buffer size to each chip, but
>> +	 * a different size can be specified with devtype_data->sfa_size.
>> +	 * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the
>> +	 * top (end) of these four regions.
>>   	 */
>> -	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
>> -		    base + QUADSPI_SFA1AD);
>> -	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
>> -		    base + QUADSPI_SFA2AD);
>> -	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
>> -		    base + QUADSPI_SFB1AD);
>> -	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
>> -		    base + QUADSPI_SFB2AD);
>> +	size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
>> +	qspi_writel(q, addr_offset + 1 * size, base + QUADSPI_SFA1AD);
>> +	qspi_writel(q, addr_offset + 2 * size, base + QUADSPI_SFA2AD);
>> +	qspi_writel(q, addr_offset + 3 * size, base + QUADSPI_SFB1AD);
>> +	qspi_writel(q, addr_offset + 4 * size, base + QUADSPI_SFB2AD);
>>
>>   	q->selected = -1;
>>
>> --
>> 2.43.0
>>


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[PATCH v2 7/9] spi: fsl-qspi: support the SpacemiT K1 SoC

[Alex Elder]

Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
enabled.

Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
defining the device type data for its QSPI implementation.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
v2: - A continued line the Kconfig file is now aligned

 drivers/spi/Kconfig        |  3 ++-
 drivers/spi/spi-fsl-qspi.c | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4d8f00c850c14..592d46c9998bb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -435,7 +435,8 @@ config SPI_FSL_LPSPI
 
 config SPI_FSL_QUADSPI
 	tristate "Freescale QSPI controller"
-	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \
+		   ARCH_SPACEMIT || COMPILE_TEST
 	depends on HAS_IOMEM
 	help
 	  This enables support for the Quad SPI controller in master mode.
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index a474d1b341b6a..d4b007e8172b2 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -268,6 +268,15 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
 	.little_endian = true,
 };
 
+static const struct fsl_qspi_devtype_data spacemit_k1_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_256,
+	.ahb_buf_size = SZ_512,
+	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE,
+	.little_endian = true,
+};
+
 struct fsl_qspi {
 	void __iomem *iobase;
 	void __iomem *ahb_addr;
@@ -1003,6 +1012,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
 	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
 	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
 	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
+	{ .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.43.0


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Re: [PATCH v2 7/9] spi: fsl-qspi: support the SpacemiT K1 SoC

[han.xu]

On 25/10/23 12:59PM, Alex Elder wrote:
> Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
> enabled.
> 
> Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
> defining the device type data for its QSPI implementation.
> 
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - A continued line the Kconfig file is now aligned
> 
>  drivers/spi/Kconfig        |  3 ++-
>  drivers/spi/spi-fsl-qspi.c | 10 ++++++++++
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 4d8f00c850c14..592d46c9998bb 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -435,7 +435,8 @@ config SPI_FSL_LPSPI
>  
>  config SPI_FSL_QUADSPI
>  	tristate "Freescale QSPI controller"
> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \
> +		   ARCH_SPACEMIT || COMPILE_TEST
>  	depends on HAS_IOMEM
>  	help
>  	  This enables support for the Quad SPI controller in master mode.
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index a474d1b341b6a..d4b007e8172b2 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -268,6 +268,15 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
>  	.little_endian = true,
>  };
>  
> +static const struct fsl_qspi_devtype_data spacemit_k1_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_256,
> +	.ahb_buf_size = SZ_512,

Do you need to set the new sfa_size here for multiples of 1KB requirement?

> +	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE,
> +	.little_endian = true,
> +};
> +
>  struct fsl_qspi {
>  	void __iomem *iobase;
>  	void __iomem *ahb_addr;
> @@ -1003,6 +1012,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
>  	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
>  	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
>  	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
> +	{ .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> -- 
> 2.43.0
> 

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Re: [PATCH v2 7/9] spi: fsl-qspi: support the SpacemiT K1 SoC

[Alex Elder]

On 10/23/25 2:56 PM, han.xu wrote:
> On 25/10/23 12:59PM, Alex Elder wrote:
>> Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
>> enabled.
>>
>> Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
>> defining the device type data for its QSPI implementation.
>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> v2: - A continued line the Kconfig file is now aligned
>>
>>   drivers/spi/Kconfig        |  3 ++-
>>   drivers/spi/spi-fsl-qspi.c | 10 ++++++++++
>>   2 files changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index 4d8f00c850c14..592d46c9998bb 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -435,7 +435,8 @@ config SPI_FSL_LPSPI
>>   
>>   config SPI_FSL_QUADSPI
>>   	tristate "Freescale QSPI controller"
>> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
>> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \
>> +		   ARCH_SPACEMIT || COMPILE_TEST
>>   	depends on HAS_IOMEM
>>   	help
>>   	  This enables support for the Quad SPI controller in master mode.
>> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
>> index a474d1b341b6a..d4b007e8172b2 100644
>> --- a/drivers/spi/spi-fsl-qspi.c
>> +++ b/drivers/spi/spi-fsl-qspi.c
>> @@ -268,6 +268,15 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
>>   	.little_endian = true,
>>   };
>>   
>> +static const struct fsl_qspi_devtype_data spacemit_k1_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_256,
>> +	.ahb_buf_size = SZ_512,
> 
> Do you need to set the new sfa_size here for multiples of 1KB requirement?

Wow, yes.  I'm very sorry, I shouldn't have sent this series
out so soon.  I'm not at home and am not using my normal
development machine.  But importantly I admit to not testing
this on the target hardware before sending.

I won't do that again.

					-Alex

> 
>> +	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
>> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE,
>> +	.little_endian = true,
>> +};
>> +
>>   struct fsl_qspi {
>>   	void __iomem *iobase;
>>   	void __iomem *ahb_addr;
>> @@ -1003,6 +1012,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
>>   	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
>>   	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
>>   	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
>> +	{ .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, },
>>   	{ /* sentinel */ }
>>   };
>>   MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
>> -- 
>> 2.43.0
>>


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Re: [PATCH v2 7/9] spi: fsl-qspi: support the SpacemiT K1 SoC

[Frank Li]

On Thu, Oct 23, 2025 at 12:59:19PM -0500, Alex Elder wrote:
> Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
> enabled.
>
> Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
> defining the device type data for its QSPI implementation.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> v2: - A continued line the Kconfig file is now aligned
>
>  drivers/spi/Kconfig        |  3 ++-
>  drivers/spi/spi-fsl-qspi.c | 10 ++++++++++
>  2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 4d8f00c850c14..592d46c9998bb 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -435,7 +435,8 @@ config SPI_FSL_LPSPI
>
>  config SPI_FSL_QUADSPI
>  	tristate "Freescale QSPI controller"
> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \
> +		   ARCH_SPACEMIT || COMPILE_TEST
>  	depends on HAS_IOMEM
>  	help
>  	  This enables support for the Quad SPI controller in master mode.
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> index a474d1b341b6a..d4b007e8172b2 100644
> --- a/drivers/spi/spi-fsl-qspi.c
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -268,6 +268,15 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
>  	.little_endian = true,
>  };
>
> +static const struct fsl_qspi_devtype_data spacemit_k1_data = {
> +	.rxfifo = SZ_128,
> +	.txfifo = SZ_256,
> +	.ahb_buf_size = SZ_512,
> +	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE,
> +	.little_endian = true,

did you test your code? miss set sfa_size here.

Frank

> +};
> +
>  struct fsl_qspi {
>  	void __iomem *iobase;
>  	void __iomem *ahb_addr;
> @@ -1003,6 +1012,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
>  	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
>  	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
>  	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
> +	{ .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> --
> 2.43.0
>

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Re: [PATCH v2 7/9] spi: fsl-qspi: support the SpacemiT K1 SoC

[Alex Elder]

On 10/23/25 6:41 PM, Frank Li wrote:
> On Thu, Oct 23, 2025 at 12:59:19PM -0500, Alex Elder wrote:
>> Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
>> enabled.
>>
>> Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
>> defining the device type data for its QSPI implementation.
>>
>> Signed-off-by: Alex Elder <elder@riscstar.com>
>> ---
>> v2: - A continued line the Kconfig file is now aligned
>>
>>   drivers/spi/Kconfig        |  3 ++-
>>   drivers/spi/spi-fsl-qspi.c | 10 ++++++++++
>>   2 files changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index 4d8f00c850c14..592d46c9998bb 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -435,7 +435,8 @@ config SPI_FSL_LPSPI
>>
>>   config SPI_FSL_QUADSPI
>>   	tristate "Freescale QSPI controller"
>> -	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
>> +	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \
>> +		   ARCH_SPACEMIT || COMPILE_TEST
>>   	depends on HAS_IOMEM
>>   	help
>>   	  This enables support for the Quad SPI controller in master mode.
>> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
>> index a474d1b341b6a..d4b007e8172b2 100644
>> --- a/drivers/spi/spi-fsl-qspi.c
>> +++ b/drivers/spi/spi-fsl-qspi.c
>> @@ -268,6 +268,15 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
>>   	.little_endian = true,
>>   };
>>
>> +static const struct fsl_qspi_devtype_data spacemit_k1_data = {
>> +	.rxfifo = SZ_128,
>> +	.txfifo = SZ_256,
>> +	.ahb_buf_size = SZ_512,
>> +	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
>> +	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE,
>> +	.little_endian = true,
> 
> did you test your code? miss set sfa_size here.

I confessed earlier I did not, and I'm very sorry about that.
No future version will be sent until it's all tested.

					-Alex
> 
> Frank
> 
>> +};
>> +
>>   struct fsl_qspi {
>>   	void __iomem *iobase;
>>   	void __iomem *ahb_addr;
>> @@ -1003,6 +1012,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
>>   	{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
>>   	{ .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, },
>>   	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
>> +	{ .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, },
>>   	{ /* sentinel */ }
>>   };
>>   MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
>> --
>> 2.43.0
>>


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[PATCH v2 8/9] riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3

[Alex Elder]

Define DTS nodes to enable support for QSPI on the K1 SoC, including the
pin control configuration used.  Enable QSPI on the Banana Pi BPI-F3 board.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
 .../boot/dts/spacemit/k1-bananapi-f3.dts      |  6 ++++++
 arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi  | 21 +++++++++++++++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi          | 16 ++++++++++++++
 3 files changed, 43 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 33ca816bfd4b3..2f3750f7fd6f3 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -258,6 +258,12 @@ dldo7 {
 	};
 };
 
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_cfg>;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_2_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index 4eef81d583f3d..e922e05ff856d 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -73,6 +73,27 @@ i2c8-0-pins {
 		};
 	};
 
+	qspi_cfg: qspi-cfg {
+		qspi-pins {
+			pinmux = <K1_PADCONF(98, 0)>,    /* QSPI_DATA3 */
+				 <K1_PADCONF(99, 0)>,    /* QSPI_DATA2 */
+				 <K1_PADCONF(100, 0)>,   /* QSPI_DATA1 */
+				 <K1_PADCONF(101, 0)>,   /* QSPI_DATA0 */
+				 <K1_PADCONF(102, 0)>;   /* QSPI_CLK */
+
+			bias-disable;
+			drive-strength = <19>;
+			power-source = <3300>;
+		};
+
+		qspi-cs1-pins {
+			pinmux = <K1_PADCONF(103, 0)>;   /* QSPI_CS1 */
+			bias-pull-up = <0>;
+			drive-strength = <19>;
+			power-source = <3300>;
+		};
+	};
+
 	/omit-if-no-ref/
 	uart0_0_cfg: uart0-0-cfg {
 		uart0-0-pins {
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index af35f9cd64351..47f97105bff0b 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -823,6 +823,22 @@ uart9: serial@d4017800 {
 				status = "disabled";
 			};
 
+			qspi: spi@d420c000 {
+				compatible = "spacemit,k1-qspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0xd420c000 0x0 0x1000>,
+				      <0x0 0xb8000000 0x0 0xc00000>;
+				reg-names = "QuadSPI", "QuadSPI-memory";
+				clocks = <&syscon_apmu CLK_QSPI_BUS>,
+					 <&syscon_apmu CLK_QSPI>;
+				clock-names = "qspi_en", "qspi";
+				resets = <&syscon_apmu RESET_QSPI>,
+					 <&syscon_apmu RESET_QSPI_BUS>;
+				interrupts = <117>;
+				status = "disabled";
+			};
+
 			/* sec_uart1: 0xf0612000, not available from Linux */
 		};
 
-- 
2.43.0


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[PATCH v2 9/9] riscv: defconfig: enable SPI_FSL_QUADSPI as a module

[Alex Elder]

The SpacemiT K1 SoC QSPI IP uses the Freescale driver.  Enable it as a
module in the default kernel configuration for RISC-V.

Signed-off-by: Alex Elder <elder@riscstar.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index fc2725cbca187..48afe30d42e88 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -158,6 +158,7 @@ CONFIG_I2C_DESIGNWARE_CORE=y
 CONFIG_I2C_MV64XXX=m
 CONFIG_SPI=y
 CONFIG_SPI_CADENCE_QUADSPI=m
+CONFIG_SPI_FSL_QUADSPI=m
 CONFIG_SPI_PL022=m
 CONFIG_SPI_SIFIVE=y
 CONFIG_SPI_SUN6I=y
-- 
2.43.0


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