From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB2E0C4345F for ; Tue, 23 Apr 2024 08:58:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject: Cc:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=noSgYEdovrDa13pLHfO/hmZMaCT2PlsqENYBURSe0DE=; b=A0E4IafH4CJ8rw bGVyyp4P126S4XVNiSjQ1XyraPr3KJe4o8+K37vZJwg7ZXdvVjnAiZAgvDJz1/7/3+2EES0/hEd6n ZCf0EmyIyAhpi3Lg4TlqCWW9dG7x4Xd/9FXMeRlrcuG7N/FZ9mZkTLyv4//9+aGvDWedCz6y8JOdy sk9AehE8Cdx/rkKN2ZWQX79wk9VZ4dkM9gbjZH/OYJeyvn7eY9yV5/SjOOn7cjp0fMhOo3cI9+oE/ 7mz43NrHZrJiGv4gwgyiTA/T0SV3kpcYti0H58gPzSNWG2ufcrm6mF95ocvKBHPZcneJkqh5BAiVE CcqBXzuH5H35E4b5lyBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rzByh-0000000GYgp-3W4z; Tue, 23 Apr 2024 08:58:15 +0000 Received: from madrid.collaboradmins.com ([46.235.227.194]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rzByd-0000000GYdi-11re; Tue, 23 Apr 2024 08:58:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1713862690; bh=L/PIHK5+MUSnlGJTRqiF36FvWG0X7EQOemV2hQ9TZUM=; h=Date:Cc:Subject:To:References:From:In-Reply-To:From; b=vXf+/DXaADWNVr+F5/n1bwojDoFgaDmpU/WJSb2zTdyEeWktQMCE3D7vvSnjZFabI p0fiBT+WyCSg6qrpW8BBorzpyBYvXWtXWpUg7X15fhEmR4x7dONbPl93y0Xrcq+UYI zTCYmZDav+zzqhqVDrVADzYpOo9H0OPzoIjY6VLoDnPXCCjKkxxrU40dxZ0xPxYBOZ j2/lymoEz6fxlDqa7D9lVAT3s3Z3UUw3BupJWzyl4XJS8xOnJnlPNIEAAKFhQpmhqj IWCV72eKoodxgflK0gwFSr8dLBHglenUQvmk6Zwqalalnpx7hO0EJ8rE0s42t5Lul+ 2qz2wTqJkaavg== Received: from [10.193.1.1] (broslavsky.collaboradmins.com [68.183.210.73]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: usama.anjum) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 792B23780016; Tue, 23 Apr 2024 08:58:02 +0000 (UTC) Message-ID: Date: Tue, 23 Apr 2024 13:58:32 +0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: Muhammad Usama Anjum , Andrew Jones , Anup Patel , Ajay Kaher , Albert Ou , Alexandre Ghiti , samuel.holland@sifive.com, Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, Will Deacon , x86@kernel.org Subject: Re: [PATCH v8 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions To: Atish Patra , linux-kernel@vger.kernel.org References: <20240420151741.962500-1-atishp@rivosinc.com> <20240420151741.962500-21-atishp@rivosinc.com> Content-Language: en-US From: Muhammad Usama Anjum In-Reply-To: <20240420151741.962500-21-atishp@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240423_015811_517125_D61897FB X-CRM114-Status: GOOD ( 12.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 4/20/24 8:17 PM, Atish Patra wrote: > The SBI PMU extension definition is required for upcoming SBI PMU > selftests. > > Reviewed-by: Andrew Jones > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra LGTM Reviewed-by: Muhammad Usama Anjum > --- > .../testing/selftests/kvm/include/riscv/sbi.h | 66 +++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testing/selftests/kvm/include/riscv/sbi.h > index ba04f2dec7b5..6675ca673c77 100644 > --- a/tools/testing/selftests/kvm/include/riscv/sbi.h > +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h > @@ -29,17 +29,83 @@ > enum sbi_ext_id { > SBI_EXT_BASE = 0x10, > SBI_EXT_STA = 0x535441, > + SBI_EXT_PMU = 0x504D55, > }; > > enum sbi_ext_base_fid { > SBI_EXT_BASE_PROBE_EXT = 3, > }; > +enum sbi_ext_pmu_fid { > + SBI_EXT_PMU_NUM_COUNTERS = 0, > + SBI_EXT_PMU_COUNTER_GET_INFO, > + SBI_EXT_PMU_COUNTER_CFG_MATCH, > + SBI_EXT_PMU_COUNTER_START, > + SBI_EXT_PMU_COUNTER_STOP, > + SBI_EXT_PMU_COUNTER_FW_READ, > + SBI_EXT_PMU_COUNTER_FW_READ_HI, > + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, > +}; > + > +union sbi_pmu_ctr_info { > + unsigned long value; > + struct { > + unsigned long csr:12; > + unsigned long width:6; > +#if __riscv_xlen == 32 > + unsigned long reserved:13; > +#else > + unsigned long reserved:45; > +#endif > + unsigned long type:1; > + }; > +}; > > struct sbiret { > long error; > long value; > }; > > +/** General pmu event codes specified in SBI PMU extension */ > +enum sbi_pmu_hw_generic_events_t { > + SBI_PMU_HW_NO_EVENT = 0, > + SBI_PMU_HW_CPU_CYCLES = 1, > + SBI_PMU_HW_INSTRUCTIONS = 2, > + SBI_PMU_HW_CACHE_REFERENCES = 3, > + SBI_PMU_HW_CACHE_MISSES = 4, > + SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, > + SBI_PMU_HW_BRANCH_MISSES = 6, > + SBI_PMU_HW_BUS_CYCLES = 7, > + SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, > + SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, > + SBI_PMU_HW_REF_CPU_CYCLES = 10, > + > + SBI_PMU_HW_GENERAL_MAX, > +}; > + > +/* SBI PMU counter types */ > +enum sbi_pmu_ctr_type { > + SBI_PMU_CTR_TYPE_HW = 0x0, > + SBI_PMU_CTR_TYPE_FW, > +}; > + > +/* Flags defined for config matching function */ > +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) > +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) > +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) > +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) > +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) > +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) > +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) > +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) > + > +/* Flags defined for counter start function */ > +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) > +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) > + > +/* Flags defined for counter stop function */ > +#define SBI_PMU_STOP_FLAG_RESET BIT(0) > +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) > + > struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, > unsigned long arg1, unsigned long arg2, > unsigned long arg3, unsigned long arg4, -- BR, Muhammad Usama Anjum _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv