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Sun, 21 Jun 2026 23:43:32 -0700 (PDT) Received: from blinky ([2601:647:6700:64d0::92d1]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-139add73a44sm6680306c88.13.2026.06.21.23.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 23:43:32 -0700 (PDT) Date: Sun, 21 Jun 2026 23:43:29 -0700 From: Charlie Jenkins To: Atish Patra Cc: James Clark , Rob Herring , Arnaldo Carvalho de Melo , Jiri Olsa , Will Deacon , Mark Rutland , Anup Patel , Namhyung Kim , Paul Walmsley , Krzysztof Kozlowski , Ian Rogers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition Message-ID: References: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> <20260608-counter_delegation-v6-7-285b72ed65a9@meta.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260608-counter_delegation-v6-7-285b72ed65a9@meta.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260621_234333_970395_03631DAE X-CRM114-Status: GOOD ( 19.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 08, 2026 at 11:01:21PM -0700, Atish Patra wrote: > From: Kaiwen Xue > = > This adds the scountinhibit CSR definition and S-mode accessible hpmevent > bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop > counters directly from S-mode without invoking SBI calls to M-mode. It is > also used to figure out the counters delegated to S-mode by the M-mode as > well. > = > Signed-off-by: Kaiwen Xue > Reviewed-by: Cl=E9ment L=E9ger > --- > arch/riscv/include/asm/csr.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > = > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index b4551a6cf7cb..26cb78dee2fd 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -241,6 +241,31 @@ > #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) > #define SMSTATEEN0_SSTATEEN0_SHIFT 63 > #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) > +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */ > +#ifdef CONFIG_64BIT > +#define HPMEVENT_OF (BIT_ULL(63)) > +#define HPMEVENT_MINH (BIT_ULL(62)) > +#define HPMEVENT_SINH (BIT_ULL(61)) > +#define HPMEVENT_UINH (BIT_ULL(60)) > +#define HPMEVENT_VSINH (BIT_ULL(59)) > +#define HPMEVENT_VUINH (BIT_ULL(58)) > +#else > +#define HPMEVENTH_OF (BIT_ULL(31)) > +#define HPMEVENTH_MINH (BIT_ULL(30)) > +#define HPMEVENTH_SINH (BIT_ULL(29)) > +#define HPMEVENTH_UINH (BIT_ULL(28)) > +#define HPMEVENTH_VSINH (BIT_ULL(27)) > +#define HPMEVENTH_VUINH (BIT_ULL(26)) Since these are rv32 bits for a 32-bit register, I think these should be BIT() instead of BIT_ULL() > + > +#define HPMEVENT_OF (HPMEVENTH_OF << 32) > +#define HPMEVENT_MINH (HPMEVENTH_MINH << 32) > +#define HPMEVENT_SINH (HPMEVENTH_SINH << 32) > +#define HPMEVENT_UINH (HPMEVENTH_UINH << 32) > +#define HPMEVENT_VSINH (HPMEVENTH_VSINH << 32) > +#define HPMEVENT_VUINH (HPMEVENTH_VUINH << 32) These definitions are identical to the rv64 ones, can these be removed and can you move the rv64 definitions to be global? - Charlie > +#endif > + > +#define SISELECT_SSCCFG_BASE 0x40 > = > /* mseccfg bits */ > #define MSECCFG_PMM ENVCFG_PMM > @@ -322,6 +347,7 @@ > #define CSR_SCOUNTEREN 0x106 > #define CSR_SENVCFG 0x10a > #define CSR_SSTATEEN0 0x10c > +#define CSR_SCOUNTINHIBIT 0x120 > #define CSR_SSCRATCH 0x140 > #define CSR_SEPC 0x141 > #define CSR_SCAUSE 0x142 > = > -- = > 2.53.0-Meta > = > = > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv