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Tue, 30 Jun 2026 04:11:34 -0700 (PDT) Received: from plin-1878 ([136.226.240.191]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38052f47a3dsm1541965a91.13.2026.06.30.04.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 04:11:34 -0700 (PDT) Date: Tue, 30 Jun 2026 19:11:26 +0800 From: Yu-Chien Peter Lin To: Conor Dooley Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, guodong@riscstar.com, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com Subject: Re: [RFC PATCH 2/3] dt-bindings: riscv: Add Worlds per-hart properties Message-ID: References: <20260619105834.1277302-1-peter.lin@sifive.com> <20260619105834.1277302-3-peter.lin@sifive.com> <20260622-profanity-herbs-1cc1bcf6206f@spud> <20260626-chitchat-purity-33af51f88380@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260626-chitchat-purity-33af51f88380@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260630_041136_132626_5DCB6C22 X-CRM114-Status: GOOD ( 32.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Conor, On Fri, Jun 26, 2026 at 03:36:38PM +0100, Conor Dooley wrote: > On Fri, Jun 26, 2026 at 07:47:31PM +0800, Yu-Chien Peter Lin wrote: > > Hi Conor, > > > > On Mon, Jun 22, 2026 at 06:12:47PM +0100, Conor Dooley wrote: > > > On Fri, Jun 19, 2026 at 06:58:33PM +0800, Yu-Chien Peter Lin wrote: > > > > Add per-hart DT properties for RISC-V Worlds architecture: > > > > riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These > > > > platform-defined values are primarily used by M-mode firmware > > > > to configure World ID CSRs and restrict WID usage across > > > > privilege levels. > > > > > > > > Signed-off-by: Yu-Chien Peter Lin > > > > --- > > > > .../devicetree/bindings/riscv/cpus.yaml | 21 +++++ > > > > .../devicetree/bindings/riscv/worlds.yaml | 77 +++++++++++++++++++ > > > > 2 files changed, 98 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > > index 5feeb2203050..4b5778b6d3e7 100644 > > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > > @@ -26,6 +26,7 @@ description: | > > > > allOf: > > > > - $ref: /schemas/cpu.yaml# > > > > - $ref: extensions.yaml > > > > + - $ref: worlds.yaml > > > > - if: > > > > not: > > > > properties: > > > > @@ -120,11 +121,31 @@ properties: > > > > thead systems where the vector register length is not identical on all harts, or > > > > the vlenb CSR is not available. > > > > > > > > + riscv,pmwid: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > + description: > > > > + Platform-defined M-mode World ID (WID) assigned to this hart. > > > > + minimum: 0 > > > > + maximum: 63 > > > > + > > > > + riscv,pmwidlist: > > > > + $ref: /schemas/types.yaml#/definitions/uint64 > > > > + description: > > > > + Platform-defined bitmap of M-mode World IDs (WIDs) that this hart may use. > > > > > > I don't understand what the difference is between this property and the > > > one before it are. > > > Is this one meant to be used by m-mode software to then select one which > > > will appear in riscv,pmwid? > > > > pmwid (single value) is the reset default, while pmwidlist (bitmap) > > defines the allowed set. The root-of-trust M-mode software may select > > an allowed value from the pmwidlist and write it to the mwid CSR. > > I don't understand the point of the property then. If it is the reset > default, just read it out of the register? > Unless I am missing something, it's useless to s-mode because it may > not be what m-mode chose and useless to m-mode that has access to > the csr. Smwid is optional. In the no-Smwid case: - M-mode's WID is fixed to pmwid (hardware-defined via fuse/pinstrap/SoC registers, exposed to software via riscv,pmwid DT property) - S/U-mode's WID depends on opensbi-domain configuration [1]: - If next-wid is specified: S/U use that WID (via mlwid CSR) - If next-wid is absent : S/U fall back to pmwid (M/S/U in same world) So riscv,pmwid serves two purpose: 1. Source of truth for M-mode's WID when mwid CSR doesn't exist 2. Fallback value for OpenSBI to write to mlwid when domain config is absent. [1] https://lists.infradead.org/pipermail/opensbi/2026-June/010090.html Best regards, Peter Lin > > Cheers, > Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv