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Thu, 02 Jul 2026 18:51:38 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-847cb9d80c0sm2123471b3a.54.2026.07.02.18.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 18:51:38 -0700 (PDT) Date: Fri, 3 Jul 2026 09:51:08 +0800 From: Inochi Amaoto To: Alex Elder , Manivannan Sadhasivam , Inochi Amaoto Cc: Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Christian Bruel , Vincent Guittot , Senchuan Zhang , Nam Cao , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: Re: [PATCH v2 4/5] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller Message-ID: References: <20260517014841.254085-1-inochiama@gmail.com> <20260517014841.254085-5-inochiama@gmail.com> <8010bb91-77e1-42b4-9f19-d9e70e385d00@riscstar.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8010bb91-77e1-42b4-9f19-d9e70e385d00@riscstar.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260702_185139_846463_56C87F48 X-CRM114-Status: GOOD ( 33.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jun 09, 2026 at 11:11:20AM -0500, Alex Elder wrote: > On 6/9/26 9:03 AM, Manivannan Sadhasivam wrote: > > On Sun, May 17, 2026 at 09:48:39AM +0800, Inochi Amaoto wrote: > > > Add binding support for the PCIe controller on the SpacemiT K3 SoC. > > > This controller is almost a standard Synopsys DesignWare PCIe IP, > > > with some extra link and reset state control. > > > > > > Signed-off-by: Inochi Amaoto > > > > Why can't you reuse the existing spacemit,k1-pcie-host.yaml binding? I see very > > few differences which could be added using conditionals. Also, this binding > > defines the PHY property in the controller node, which is a way backwards as we > > now prefer to define these in Root Port node as spacemit,k1-pcie-host.yaml does. > > I agree. I have another couple of comments below, including several > things that just point out what's the same and what's different. > > -Alex > A good caught, I have confirmed, they share the same topology so it can be reused. Regards, Inochi > > > > - Mani > > > > > --- > > > .../bindings/pci/spacemit,k3-pcie-host.yaml | 135 ++++++++++++++++++ > > > 1 file changed, 135 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml > > > new file mode 100644 > > > index 000000000000..46147a37a9ce > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml > > > @@ -0,0 +1,135 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: SpacemiT K3 PCI Express Host Controller > > > + > > > +maintainers: > > > + - Inochi Amaoto > > If you would like to maintain the (common) SpacemiT K1 host > controller binding I'd be OK with that. > > > > + > > > +description: > > > + The SpacemiT K3 SoC PCIe host controller is based on the Synopsys > > > + DesignWare PCIe IP. The controller uses the external MSI interrupt > > > + controller. > > > + > > > +allOf: > > > + - $ref: /schemas/pci/pci-host-bridge.yaml# > > > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > > > + > > > +properties: > > > + compatible: > > > + const: spacemit,k3-pcie > > > + > > > + reg: > > > + items: > > > + - description: DesignWare PCIe registers > > > + - description: Data Bus Interface (DBI) shadow registers > > The above is new (different from K1), as is "dbi2" as its name. > > > > + - description: ATU address space > > > + - description: PCIe configuration space > > > + - description: Link control registers > > > + > > > + reg-names: > > > + items: > > > + - const: dbi > > > + - const: dbi2 > > > + - const: atu > > > + - const: config > > > + - const: link > > > + > > > + clocks: > > Clocks and resets are the same as K1. > > > > + items: > > > + - description: DWC PCIe Data Bus Interface (DBI) clock > > > + - description: DWC PCIe application AXI-bus master interface clock > > > + - description: DWC PCIe application AXI-bus slave interface clock > > > + > > > + clock-names: > > > + items: > > > + - const: dbi > > > + - const: mstr > > > + - const: slv > > > + > > > + resets: > > > + items: > > > + - description: DWC PCIe Data Bus Interface (DBI) reset > > > + - description: DWC PCIe application AXI-bus master interface reset > > > + - description: DWC PCIe application AXI-bus slave interface reset > > > + > > > + reset-names: > > > + items: > > > + - const: dbi > > > + - const: mstr > > > + - const: slv > > > + > > > + msi-parent: true > > msi-parent and phys are not present in the K1 binding. > > > > + > > > + phys: > > > + description: > > > + PHY phandle from the Combo PHY, the lane number does not depends > > > + on this, since the number of lanes provided by Combo PHY can be > > > + 1 or 2. > > > + minItems: 1 > > > + maxItems: 6 > > > + > > > + phy-names: > > > + minItems: 1 > > > + maxItems: 6 > > > + > > The following property is the same as K1. > > > > + spacemit,apmu: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + description: > > > + A phandle that refers to the APMU system controller, whose regmap is > > > + used in managing resets and link state, along with and offset of its > > > + reset control register. > > > + items: > > > + - items: > > > + - description: phandle to APMU system controller > > > + - description: register offset > > > + > > > +required: > > > + - clocks > > > + - clock-names > > > + - resets > > > + - reset-names > > > + - msi-parent > > > + - spacemit,apmu > > > + > > > +unevaluatedProperties: false > > > + > > > +examples: > > > + - | > > > + #include > > > + > > > + soc { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + pcie@80000000 { > > > + compatible = "spacemit,k3-pcie"; > > > + reg = <0x0 0x80000000 0x0 0x00001000>, > > > + <0x0 0x80100000 0x0 0x00001000>, > > > + <0x0 0x80300000 0x0 0x00003f20>, > > > + <0x11 0x00000000 0x0 0x00010000>, > > > + <0x0 0x82900000 0x0 0x00001000>; > > > + reg-names = "dbi", "dbi2", "atu", "config", "link"; > > > + device_type = "pci"; > > > + #address-cells = <3>; > > > + #size-cells = <2>; > > > + clocks = <&syscon_apmu 89>, > > > + <&syscon_apmu 56>, > > > + <&syscon_apmu 57>; > > > + clock-names = "dbi", "mstr", "slv"; > > > + msi-parent = <&simsic>; > > > + ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, > > > + <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, > > > + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; > > > + resets = <&syscon_apmu 76>, > > > + <&syscon_apmu 78>, > > > + <&syscon_apmu 77>; > > > + reset-names = "dbi", "mstr", "slv"; > > > + linux,pci-domain = <0>; > > > + spacemit,apmu = <&syscon_apmu 0x1f0>; > > > + }; > > > + }; > > > + > > > -- > > > 2.54.0 > > > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv