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Tue, 04 Aug 2026 01:25:35 -0700 (PDT) Received: from plin-1878 ([136.226.240.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0aa4930e1sm2426415ad.41.2026.08.04.01.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Aug 2026 01:25:35 -0700 (PDT) Date: Tue, 4 Aug 2026 16:25:29 +0800 From: Yu-Chien Peter Lin To: Nick Kossifidis Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr Subject: Re: [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Message-ID: References: <20260729163908.249838-1-peter.lin@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260804_012536_865800_155A196C X-CRM114-Status: GOOD ( 23.14 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Nick, Thanks for the questions. On Fri, Jul 31, 2026 at 04:43:56AM +0300, Nick Kossifidis wrote: > Hello Peter, > > On 7/29/26 19:39, Yu-Chien Peter Lin wrote: > > Add device tree bindings for RISC-V Worlds, a standard extension that tags > > every transaction with a World ID for fine-grained isolation. SiFive's > > WorldGuard Checker is a hardware firewall in the system interconnect that > > inspects transaction WIDs and enforces per-World access policies on memory > > and MMIO devices. > > > > wgChecker specification reference: > > https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf > > > > Yu-Chien Peter Lin (3): > > dt-bindings: riscv: Add Worlds ISA extensions > > dt-bindings: riscv: Add Worlds per-hart properties > > dt-bindings: sifive: Add WorldGuard Checker > > > > .../devicetree/bindings/riscv/cpus.yaml | 61 +++ > > .../devicetree/bindings/riscv/extensions.yaml | 53 +++ > > .../devicetree/bindings/riscv/worlds.yaml | 86 +++++ > > .../bindings/sifive/sifive,wgchecker2.yaml | 356 ++++++++++++++++++ > > 4 files changed, 556 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml > > create mode 100644 Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml > > > > What's the plan for this and why do we need Linux-specific dt bindings ? > This looks more like a set of firmware specific bindings, like OpenSBI > domains for example (https://github.com/riscv-software-src/opensbi/blob/master/docs/domain_support.md). > I understand adding the ISA extensions in the list (although the fast track > is still underway, it's not ratified yet), but the rest don't make sense, > not yet at least. How do you plan to use pmlwidlist on Linux to associate > processes to wids ? Do you plan on adding a driver for the wg checker (and > the markers that you mention) on Linux ? Do you ever expect Linux to run > under trustedwid ? We do not currently plan to implement a wgChecker driver in the Linux kernel which holds the untrusted WID; wgChecker slot configuration is handled by OpenSBI only at boot-time. The intention here is providing a standardized device-tree format for describing wgChecker hardware and protection policy, usable consistently across Linux ecosystem (OpenSBI and possibly OP-TEE). Thanks, Peter Lin > > Regards, > Nick _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv