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Mon, 10 Aug 2026 19:24:06 -0700 (PDT) Received: from plin-1878 ([136.226.240.195]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-392d4051b98sm1572918a91.1.2026.08.10.19.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 19:24:06 -0700 (PDT) Date: Tue, 11 Aug 2026 10:23:56 +0800 From: Yu-Chien Peter Lin To: Conor Dooley Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, guodong@riscstar.com, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Message-ID: References: <20260729163908.249838-1-peter.lin@sifive.com> <20260729163908.249838-2-peter.lin@sifive.com> <20260810-penpal-aluminum-772319e5fc10@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260810-penpal-aluminum-772319e5fc10@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260810_192408_176891_46763C9B X-CRM114-Status: GOOD ( 16.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Aug 10, 2026 at 05:25:08PM +0100, Conor Dooley wrote: > On Thu, Jul 30, 2026 at 12:39:06AM +0800, Yu-Chien Peter Lin wrote: > > Add DT bindings for five RISC-V Worlds ISA extensions > > that implement World ID tagging for hardware-enforced > > context isolation. Also, add checks for extension > > dependency requirements. > > > > Signed-off-by: Yu-Chien Peter Lin > > --- > > .../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++ > > 1 file changed, 53 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 2b0a8a93bb21..7a57191a0293 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -193,12 +193,35 @@ properties: > > ratified at commit d70011dde6c2 ("Update to ratified state") > > of riscv-j-extension. > > > > + - const: smlwid > > + description: | > > + The standard Smlwid extension for M-mode control of lower > > + privilege World ID via the mlwid CSR as ratified at commit > > + TBD ("TBD") of riscv-worlds. > > > btw, when you send a v3 of this please mark it RFC, since you're using > placeholders here for the commit hashes of the extension being frozen. Sure, will do. Thanks, Peter Lin > > Cheers, > Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv