From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: Conor Dooley <conor@kernel.org>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
samuel.holland@sifive.com, dlan@kernel.org,
dfustini@oss.tenstorrent.com, michal.simek@amd.com,
junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com,
akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn,
luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn,
nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com,
greentime.hu@sifive.com, robin.randhawa@sifive.com,
scott@riscstar.com, dave.patel@riscstar.com,
raymond.mao@riscstar.com, anup@brainfault.org,
pawandeep.oza@oss.qualcomm.com
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions
Date: Tue, 11 Aug 2026 16:24:52 +0800 [thread overview]
Message-ID: <anrcVIoupzPVA74B@plin-1878> (raw)
In-Reply-To: <20260810-penpal-aluminum-772319e5fc10@spud>
On Mon, Aug 10, 2026 at 05:25:08PM +0100, Conor Dooley wrote:
> On Thu, Jul 30, 2026 at 12:39:06AM +0800, Yu-Chien Peter Lin wrote:
> > Add DT bindings for five RISC-V Worlds ISA extensions
> > that implement World ID tagging for hardware-enforced
> > context isolation. Also, add checks for extension
> > dependency requirements.
> >
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> > ---
> > .../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++
> > 1 file changed, 53 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 2b0a8a93bb21..7a57191a0293 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -193,12 +193,35 @@ properties:
> > ratified at commit d70011dde6c2 ("Update to ratified state")
> > of riscv-j-extension.
> >
> > + - const: smlwid
> > + description: |
> > + The standard Smlwid extension for M-mode control of lower
> > + privilege World ID via the mlwid CSR as ratified at commit
> > + TBD ("TBD") of riscv-worlds.
Also, I will follow alphabetical order in the next version.
Regards,
Peter Lin
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next prev parent reply other threads:[~2026-08-11 8:25 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-08-10 16:25 ` Conor Dooley
2026-08-11 2:23 ` Yu-Chien Peter Lin
2026-08-11 8:24 ` Yu-Chien Peter Lin [this message]
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 18:06 ` Rob Herring (Arm)
2026-08-07 7:57 ` Yu-Chien Peter Lin
2026-07-30 7:30 ` Krzysztof Kozlowski
2026-08-11 9:31 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 18:07 ` Rob Herring (Arm)
2026-08-11 9:36 ` Yu-Chien Peter Lin
2026-07-30 7:35 ` Krzysztof Kozlowski
2026-07-30 7:37 ` Krzysztof Kozlowski
2026-08-11 9:42 ` Yu-Chien Peter Lin
2026-07-30 17:36 ` Conor Dooley
2026-08-11 9:59 ` Yu-Chien Peter Lin
2026-08-11 9:41 ` Yu-Chien Peter Lin
2026-07-31 1:43 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Nick Kossifidis
2026-08-04 8:25 ` Yu-Chien Peter Lin
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