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spf=pass smtp.mailfrom=me@ziyao.cc; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1789106942; s=zmail; d=ziyao.cc; i=me@ziyao.cc; h=Date:Date:From:From:To:To:Cc:Cc:Subject:Subject:Message-ID:MIME-Version:Content-Type:In-Reply-To:Message-Id:Reply-To; bh=BzCWIm9SHWefUAfRNuRqKetUCaMam98cRazVY0T6n/Q=; b=EKdB/M5YRvPU4+d8P1+0AhgvguH8AVpGPwkMhjr+oAKdaz9S/KDjP3JkjXaerv4T NcbFZiYWds6qL9sDauM0YUpxpUAh2fnAMC0HyvxzAfF60bkx76FTbC2cA8hDqbrHclM Jxph0tnkk2lAiivc08DiQjMWfOyMwspreIS5IBqA= Received: by mx.zohomail.com with SMTPS id 1789106940627378.773449342185; Thu, 10 Sep 2026 23:09:00 -0700 (PDT) Date: Fri, 11 Sep 2026 06:08:46 +0000 From: Yao Zi To: "Troy Mitchell" , "Yao Zi" , "Stephen Boyd" , "Brian Masney" , "Jerome Brunet" , "Yixun Lan" , "Alex Elder" , "Inochi Amaoto" , "Haylen Chu" Cc: , , , Subject: Re: [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs Message-ID: References: <20260909-spacemit-pll-init-v1-0-b3065ad5a4ac@linux.spacemit.com> <20260909-spacemit-pll-init-v1-4-b3065ad5a4ac@linux.spacemit.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/289.97.79 X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260911_070925_200173_1D4DDDA4 X-CRM114-Status: GOOD ( 16.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Sep 11, 2026 at 10:02:47AM +0800, Troy Mitchell wrote: > On Thu Sep 10, 2026 at 9:31 PM +08, Yao Zi wrote: > > On Wed, Sep 09, 2026 at 10:07:04PM +0800, Troy Mitchell wrote: > >> CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left > >> running by firmware can have a zero prepare count, so this flag alone > >> cannot prevent set_rate() from reprogramming a live PLL. > > > > Would it be a better idea to simply turn off the PLL before reprogramming, > > since protected by CLK_SET_RATE_GATE, re-programming never happens when > > the PLL is required by downstream? This also seems to be simpler. > Then assigned-clock-rates on the PLL provider node? Protecting PLL from rate-changing when it's enabled, and re-programming the PLL to a recommended rate, are separate goals. This review comment only focuses on the former (i.e. changes in this patch). > I tested this > on K3: .set_rate() was called during provider registration, with PLL3's > prepare count still zero while the CPUs were running on it. Disabling > PLL3 hung the board. CLK_SET_RATE_GATE therefore does not protect users > that CCF has not yet accounted for. I think it's caused by asynchronous probing. The APMU controller might probe and register clocks after the PLL one, so the prepare/enable counters of the PLLs might not match the reality during the gap. > > -- > Troy Mitchell > Best regards, Yao Zi _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv