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Fri, 02 Oct 2026 14:47:41 -0700 (PDT) Received: from redhat.com ([69.43.42.202]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93e4e96acebsm97276885a.21.2026.10.02.14.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2026 14:47:40 -0700 (PDT) Date: Fri, 2 Oct 2026 17:47:38 -0400 From: Brian Masney To: Conor Dooley Cc: Changhuang Liang , Michael Turquette , Jerome Brunet , Stephen Boyd , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Kees Cook , "Gustavo A . R . Silva" , Richard Cochran , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng Subject: Re: [PATCH v5 00/23] Add basic clocks and resets for JHB100 SoC Message-ID: References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> <20260930-grafting-undertake-ff3e01060284@spud> <20261002-amigo-joyfully-6894bdfa17e3@spud> <20261002-doorbell-recycler-f386e3b8d5a4@spud> MIME-Version: 1.0 In-Reply-To: <20261002-doorbell-recycler-f386e3b8d5a4@spud> User-Agent: Mutt/2.4.2 (2026-08-30) X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 0wo3PONdmbMGPy-7RUKrLkzK8w9JtKZ2DZl_AEl1PcM_1790977663 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261002_144746_566565_78E33024 X-CRM114-Status: GOOD ( 18.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Conor, On Fri, Oct 02, 2026 at 09:26:34PM +0100, Conor Dooley wrote: > > btw, will you be at LPC or OSSEU? Yes, I'll be at LPC. I'm giving a clk talk the second day, so you can find me there if we don't cross paths before then. > ... As I went about aligning more ducks, I recalled that the syscon/pll > series also depends on some of the binding header files in this series. > > I've made another tag with an additional binding that you'll need to > apply the clock patches in this series: > https://lore.kernel.org/all/20260828095608.19955-2-changhuang.liang@starfivetech.com/ > > This tag will actually appear in linux-next as of the next iteration, > because the socinfo driver I will definitely submit as 7.4 material. > > Thanks, > Conor. > > The following changes since commit cee9395acd8043be0644b25c34bfa86623f2b935: > > Linux 7.3-rc1 (2026-08-30 13:34:40 -0700) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ clk-starfive-jhb100-plus-soc-header > > for you to fetch changes up to c4a545d3e428e9600d670fa8a08098b7bc82d5ec: > > dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules (2026-10-02 21:17:31 +0100) > > ---------------------------------------------------------------- > jhb100 clock binding + syscon binding shared tag > > This is a second shared tag for the Starfive jhb100 clock bindings, between > the riscv soc tree and clock tree. > > Signed-off-by: Conor Dooley > > ---------------------------------------------------------------- > Changhuang Liang (8): > dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator > dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator > dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator > dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator > dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator > dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator > dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator > dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules Pulled into clk-next. Brian _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv