From: Sean Anderson <seanga2@gmail.com>
To: Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: Anup Patel <Anup.Patel@wdc.com>
Subject: Re: [PATCH v2 6/9] riscv: Add Kendryte K210 device tree
Date: Thu, 12 Mar 2020 14:16:30 -0400 [thread overview]
Message-ID: <b175cd33-7143-164b-07fb-468a1e727180@gmail.com> (raw)
In-Reply-To: <20200312051107.1454880-7-damien.lemoal@wdc.com>
On 3/12/20 1:11 AM, Damien Le Moal wrote:
> Add a generic device tree for Kendryte K210 SoC based boards. This (for
> now) very simple device tree works for the Kendryte KD233 development
> board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.
>
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/kendryte/Makefile | 2 +
> arch/riscv/boot/dts/kendryte/k210.dts | 23 +++++
> arch/riscv/boot/dts/kendryte/k210.dtsi | 117 +++++++++++++++++++++++++
> include/dt-bindings/clock/k210-clk.h | 20 +++++
> 5 files changed, 163 insertions(+)
> create mode 100644 arch/riscv/boot/dts/kendryte/Makefile
> create mode 100644 arch/riscv/boot/dts/kendryte/k210.dts
> create mode 100644 arch/riscv/boot/dts/kendryte/k210.dtsi
> create mode 100644 include/dt-bindings/clock/k210-clk.h
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 0bf2669aa12d..87815557f2db 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,4 +3,5 @@ ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"")
> obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
> else
> subdir-y += sifive
> +subdir-y += kendryte
> endif
> diff --git a/arch/riscv/boot/dts/kendryte/Makefile b/arch/riscv/boot/dts/kendryte/Makefile
> new file mode 100644
> index 000000000000..815444e69e89
> --- /dev/null
> +++ b/arch/riscv/boot/dts/kendryte/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_KENDRYTE) += k210.dtb
> diff --git a/arch/riscv/boot/dts/kendryte/k210.dts b/arch/riscv/boot/dts/kendryte/k210.dts
> new file mode 100644
> index 000000000000..0d1f28fce6b2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/kendryte/k210.dts
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> + */
> +
> +/dts-v1/;
> +
> +#include "k210.dtsi"
> +
> +/ {
> + model = "Kendryte K210 generic";
> + compatible = "kendryte,k210";
> +
> + chosen {
> + bootargs = "earlycon console=ttySIF0";
> + stdout-path = "serial0";
> + };
> +};
> +
> +&uarths0 {
> + status = "okay";
> +};
> +
> diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi b/arch/riscv/boot/dts/kendryte/k210.dtsi
> new file mode 100644
> index 000000000000..88f28a3fd337
> --- /dev/null
> +++ b/arch/riscv/boot/dts/kendryte/k210.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
> + * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> + */
> +#include <dt-bindings/clock/k210-clk.h>
> +
> +/ {
> + /*
> + * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
> + * wide, and the upper half of all addresses is ignored.
> + */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "kendryte,k210";
> +
> + aliases {
> + serial0 = &uarths0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <7800000>;
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + reg = <0>;
> + compatible = "kendryte,k210", "sifive,rocket0", "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "none";
> + i-cache-size = <0x8000>;
> + i-cache-block-size = <64>;
> + d-cache-size = <0x8000>;
> + d-cache-block-size = <64>;
> + clocks = <&sysctl K210_CLK_CPU>;
> + clock-frequency = <390000000>;
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + reg = <1>;
> + compatible = "kendryte,k210", "sifive,rocket0", "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "none";
Perhaps add a comment? The mmu is still sv39, even if the kernel is NOMMU.
> + i-cache-size = <0x8000>;
> + i-cache-block-size = <64>; /* bogus */
These comments should be removed to match the bindings above.
> + d-cache-size = <0x8000>;
> + d-cache-block-size = <64>; /* bogus */
> + clocks = <&sysctl K210_CLK_CPU>;
> + clock-frequency = <390000000>;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + };
> + };
> + };
> +
> + sram: memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x400000>,
> + <0x80400000 0x200000>,
> + <0x80600000 0x200000>;
> + reg-names = "sram0", "sram1", "aisram";
> + };
> +
> + clocks {
> + in0: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "kendryte,k210-soc", "simple-bus";
> + ranges;
> + interrupt-parent = <&plic0>;
> +
> + sysctl: sysctl@50440000 {
> + compatible = "kendryte,k210-sysctl", "syscon";
> + reg = <0x50440000 0x1000>;
> + #clock-cells = <1>;
> + };
Still think this should be modeled as an mfd.
> +
> + clint0: interrupt-controller@2000000 {
> + compatible = "riscv,clint0";
> + reg = <0x2000000 0xC000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>;
> + clocks = <&sysctl K210_CLK_ACLK>;
> + };
> +
> + plic0: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "kendryte,k210-plic0", "riscv,plic0";
> + reg = <0xC000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
> + <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
> + riscv,ndev = <65>;
> + riscv,max-priority = <7>;
> + };
> +
> + uarths0: serial@38000000 {
> + compatible = "kendryte,k210-uarths", "sifive,uart0";
> + reg = <0x38000000 0x1000>;
> + interrupts = <33>;
> + clocks = <&sysctl K210_CLK_CPU>;
> + };
> + };
> +};
> diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h
> new file mode 100644
> index 000000000000..5a2fd64d1a49
> --- /dev/null
> +++ b/include/dt-bindings/clock/k210-clk.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
> + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
> + */
> +#ifndef K210_CLK_H
> +#define K210_CLK_H
> +
> +/*
> + * Arbitrary identifiers for clocks.
> + * The structure is: in0 -> pll0 -> aclk -> cpu
> + *
> + * Since we use the hardware defaults for now, set all these to the same clock.
> + */
> +#define K210_CLK_PLL0 0
> +#define K210_CLK_PLL1 0
> +#define K210_CLK_ACLK 0
> +#define K210_CLK_CPU 0
> +
> +#endif /* K210_CLK_H */
>
--Sean
next prev parent reply other threads:[~2020-03-12 18:16 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 5:10 [PATCH v2 0/9] Kendryte k210 SoC boards support Damien Le Moal
2020-03-12 5:10 ` [PATCH v2 1/9] riscv: Unaligned load/store handling for M_MODE Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 2/9] riscv: Add BUILTIN_DTB support Damien Le Moal
2020-03-12 20:03 ` Atish Patra
2020-03-12 5:11 ` [PATCH v2 3/9] riscv: Add SOC early init support Damien Le Moal
2020-03-12 18:21 ` Sean Anderson
2020-03-13 5:52 ` Damien Le Moal
2020-03-12 19:50 ` Atish Patra
2020-03-12 20:53 ` Atish Patra
2020-03-13 6:42 ` Damien Le Moal
2020-03-13 21:10 ` Atish Patra
2020-03-16 0:34 ` Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 4/9] riscv: Add Kendryte K210 SoC support Damien Le Moal
2020-03-12 18:19 ` Sean Anderson
2020-03-13 5:43 ` Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 5/9] riscv: Select required drivers for Kendryte SOC Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 6/9] riscv: Add Kendryte K210 device tree Damien Le Moal
2020-03-12 18:16 ` Sean Anderson [this message]
2020-03-13 5:29 ` Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 7/9] riscv: Kendryte K210 default config Damien Le Moal
2020-03-12 19:03 ` Atish Patra
2020-03-13 5:52 ` Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 8/9] riscv: create a loader.bin boot image for Kendryte SoC Damien Le Moal
2020-03-12 5:11 ` [PATCH v2 9/9] riscv: Do not initialize PMP on " Damien Le Moal
2020-03-12 15:20 ` Sean Anderson
2020-03-12 18:10 ` Atish Patra
2020-03-12 18:14 ` Sean Anderson
2020-03-12 18:29 ` Atish Patra
2020-03-12 18:49 ` Sean Anderson
2020-03-12 19:12 ` Atish Patra
2020-03-12 20:09 ` Sean Anderson
2020-03-13 6:03 ` Damien Le Moal
2020-03-13 5:40 ` Anup Patel
2020-03-13 5:25 ` Damien Le Moal
2020-03-13 5:47 ` Atish Patra
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