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X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221108_054239_002414_6D211C20 X-CRM114-Status: GOOD ( 17.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Nov 8, 2022, at 14:32, Conor Dooley wrote: > On Tue, Nov 08, 2022 at 01:51:37PM +0100, Arnd Bergmann wrote: >> On Mon, Nov 7, 2022, at 19:31, Conor Dooley wrote: >> >> I'd probably make separate entries here, at least for the >> drivers/soc/microchip directory, I can see that being shared with >> architectures other than RISC-V in the future > > (Added Nicolas to CC so that he's in the loop) > Uh sure. It'd crossed my mind, but I filed it away in the "may happen > some day" category. The arm stuff is going via the atmel directory at > the moment so I was operating on the basis of "do it this way until > something changes". > Splitting is fine by me. As things stand, anything drivers/soc/microchip > already CCs the linux-riscv list so maybe that can change alongside > this. Right, but I suppose there is a good chance of having more crossover between microchip riscv/arm/mips drivers in the future, and others like Renesas already have drivers/soc/ subdirectories that are shared. > > The one I was wondering about but forgot to mention was: > Documentation/devicetree/bindings/riscv/ > > It's mostly definitions of cpu, soc and board compatibles, so I figure > it could go with the dt stuff - and it's covered by the generic RISC-V > entry for the changes that reflect extensions etc. Right, that works. Arnd _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv