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Sat, 27 Mar 2021 14:43:50 -0400 X-MC-Unique: KTtps0L0MseR04IzHmlZFQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DF5451084C83; Sat, 27 Mar 2021 18:43:47 +0000 (UTC) Received: from llong.remote.csb (ovpn-112-10.rdu2.redhat.com [10.10.112.10]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8471E10013D6; Sat, 27 Mar 2021 18:43:46 +0000 (UTC) Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 To: guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, linux-arch@vger.kernel.org, Guo Ren , Peter Zijlstra , Will Deacon , Ingo Molnar , Arnd Bergmann , Anup Patel References: <1616868399-82848-1-git-send-email-guoren@kernel.org> <1616868399-82848-4-git-send-email-guoren@kernel.org> From: Waiman Long Organization: Red Hat Message-ID: Date: Sat, 27 Mar 2021 14:43:46 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: <1616868399-82848-4-git-send-email-guoren@kernel.org> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210327_184357_412192_48E053DE X-CRM114-Status: GOOD ( 28.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 3/27/21 2:06 PM, guoren@kernel.org wrote: > From: Guo Ren > > Some architectures don't have sub-word swap atomic instruction, > they only have the full word's one. > > The sub-word swap only improve the performance when: > NR_CPUS < 16K > * 0- 7: locked byte > * 8: pending > * 9-15: not used > * 16-17: tail index > * 18-31: tail cpu (+1) > > The 9-15 bits are wasted to use xchg16 in xchg_tail. > > Please let architecture select xchg16/xchg32 to implement > xchg_tail. > > Signed-off-by: Guo Ren > Cc: Peter Zijlstra > Cc: Will Deacon > Cc: Ingo Molnar > Cc: Waiman Long > Cc: Arnd Bergmann > Cc: Anup Patel > --- > kernel/Kconfig.locks | 3 +++ > kernel/locking/qspinlock.c | 44 +++++++++++++++++++++----------------- > 2 files changed, 27 insertions(+), 20 deletions(-) > > diff --git a/kernel/Kconfig.locks b/kernel/Kconfig.locks > index 3de8fd11873b..d02f1261f73f 100644 > --- a/kernel/Kconfig.locks > +++ b/kernel/Kconfig.locks > @@ -239,6 +239,9 @@ config LOCK_SPIN_ON_OWNER > config ARCH_USE_QUEUED_SPINLOCKS > bool > > +config ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > + bool > + > config QUEUED_SPINLOCKS > def_bool y if ARCH_USE_QUEUED_SPINLOCKS > depends on SMP > diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c > index cbff6ba53d56..54de0632c6a8 100644 > --- a/kernel/locking/qspinlock.c > +++ b/kernel/locking/qspinlock.c > @@ -163,26 +163,6 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) > WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL); > } > > -/* > - * xchg_tail - Put in the new queue tail code word & retrieve previous one > - * @lock : Pointer to queued spinlock structure > - * @tail : The new queue tail code word > - * Return: The previous queue tail code word > - * > - * xchg(lock, tail), which heads an address dependency > - * > - * p,*,* -> n,*,* ; prev = xchg(lock, node) > - */ > -static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) > -{ > - /* > - * We can use relaxed semantics since the caller ensures that the > - * MCS node is properly initialized before updating the tail. > - */ > - return (u32)xchg_relaxed(&lock->tail, > - tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET; > -} > - > #else /* _Q_PENDING_BITS == 8 */ > > /** > @@ -206,6 +186,30 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock) > { > atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val); > } > +#endif > + > +#if _Q_PENDING_BITS == 8 && !defined(CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32) > +/* > + * xchg_tail - Put in the new queue tail code word & retrieve previous one > + * @lock : Pointer to queued spinlock structure > + * @tail : The new queue tail code word > + * Return: The previous queue tail code word > + * > + * xchg(lock, tail), which heads an address dependency > + * > + * p,*,* -> n,*,* ; prev = xchg(lock, node) > + */ > +static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) > +{ > + /* > + * We can use relaxed semantics since the caller ensures that the > + * MCS node is properly initialized before updating the tail. > + */ > + return (u32)xchg_relaxed(&lock->tail, > + tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET; > +} > + > +#else > > /** > * xchg_tail - Put in the new queue tail code word & retrieve previous one I don't have any problem adding a CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32 config option to control that. One minor nit: #endif /* _Q_PENDING_BITS == 8 */ You should probably remove the comment at the trailing end of the corresponding "#endif" as it is now wrong. Cheers, Longman _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv