Re: [PATCH 0/2] riscv,aplic: support for hart indexes

Vladimir Kondratiev
2025-01-02T15:07:20Z

>Here's the text from "4.8 Interrupt delivery directly by the APLIC" of
>the AIA specification:

>"When an interrupt domain is in direct delivery mode (domaincfg.DM = 0),
>interrupts are delivered from the APLIC to harts by a unique signal to each
>hart, usually a dedicated wire. In this case, the domain’s memory-mapped
>control region contains at the end an array of interrupt delivery control (IDC)
>structures, one IDC structure per potential hart index. The first IDC structure
>is for the domain’s hart with index 0; the second is for the hart with
>index 1; etc."

>The AIA spec clearly says that for APLIC in direct mode requires
>sequential "HART index" starting from 0 so that IDC structures can
>be located using the APLIC "HART index".

Hi Anup,
I am reading same text but interpreting it differently. I understand it this way:
for every hart, there's "hart index" that may be arbitrary (unique in domain)
14-bit integer. Then IDC should be accessed using this index. I don't see
anything that prohibits sparse array of IDCs.

To support this, #4.5 "Memory-mapped control region for an interrupt domain" says:

The array of IDC structures may include some for potential hart index numbers that are not actual
hart index numbers in the domain. For example, the first IDC structure is always for hart index 0,
but 0 is not necessarily a valid index number for any hart in the domain. For each IDC structure in
the array that does not correspond to a valid hart index number in the domain, the IDC structure’s
registers may (or may not) be all read-only zeros.

This suggests 0 may be not a valid hart index, so clearly some gaps are allowed.

Thanks, Vladimir.