* [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 7:53 [PATCH v3 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
@ 2025-06-11 7:53 ` Inochi Amaoto
2025-06-11 8:19 ` Krzysztof Kozlowski
2025-06-11 7:53 ` [PATCH v3 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
` (2 subsequent siblings)
3 siblings, 1 reply; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 7:53 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Vinod Koul, Alexander Sverdlin,
Yu Yuan, Ze Huang, Thomas Bonnefille
Cc: Junhui Liu, devicetree, sophgo, linux-kernel, linux-riscv,
dmaengine, Yixun Lan, Longbin Li
Add bindings for the reset generator on the SOPHGO CV1800B
RISC-V SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
index 1d1b84575960..bd8dfa998939 100644
--- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
@@ -17,6 +17,7 @@ properties:
- sophgo,sg2044-reset
- const: sophgo,sg2042-reset
- const: sophgo,sg2042-reset
+ - const: sophgo,cv1800b-reset
reg:
maxItems: 1
--
2.49.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 7:53 ` [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
@ 2025-06-11 8:19 ` Krzysztof Kozlowski
2025-06-11 8:21 ` Krzysztof Kozlowski
2025-06-11 8:29 ` Inochi Amaoto
0 siblings, 2 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-11 8:19 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille, Junhui Liu, devicetree, sophgo,
linux-kernel, linux-riscv, dmaengine, Yixun Lan, Longbin Li
On Wed, Jun 11, 2025 at 03:53:15PM GMT, Inochi Amaoto wrote:
> Add bindings for the reset generator on the SOPHGO CV1800B
> RISC-V SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> index 1d1b84575960..bd8dfa998939 100644
> --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> @@ -17,6 +17,7 @@ properties:
> - sophgo,sg2044-reset
> - const: sophgo,sg2042-reset
> - const: sophgo,sg2042-reset
> + - const: sophgo,cv1800b-reset
Keep alphabetical order. That's enum with previous entry, btw.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 8:19 ` Krzysztof Kozlowski
@ 2025-06-11 8:21 ` Krzysztof Kozlowski
2025-06-11 8:23 ` Inochi Amaoto
2025-06-11 8:29 ` Inochi Amaoto
1 sibling, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-11 8:21 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille, Junhui Liu, devicetree, sophgo,
linux-kernel, linux-riscv, dmaengine, Yixun Lan, Longbin Li
On 11/06/2025 10:19, Krzysztof Kozlowski wrote:
> On Wed, Jun 11, 2025 at 03:53:15PM GMT, Inochi Amaoto wrote:
>> Add bindings for the reset generator on the SOPHGO CV1800B
>> RISC-V SoC.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
>> ---
>> Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
>> index 1d1b84575960..bd8dfa998939 100644
>> --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
>> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
>> @@ -17,6 +17,7 @@ properties:
>> - sophgo,sg2044-reset
>> - const: sophgo,sg2042-reset
>> - const: sophgo,sg2042-reset
>> + - const: sophgo,cv1800b-reset
>
> Keep alphabetical order. That's enum with previous entry, btw.
>
Heh, it was an enum when this was acked.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 8:21 ` Krzysztof Kozlowski
@ 2025-06-11 8:23 ` Inochi Amaoto
0 siblings, 0 replies; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 8:23 UTC (permalink / raw)
To: Krzysztof Kozlowski, Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille, Junhui Liu, devicetree, sophgo,
linux-kernel, linux-riscv, dmaengine, Yixun Lan, Longbin Li
On Wed, Jun 11, 2025 at 10:21:07AM +0200, Krzysztof Kozlowski wrote:
> On 11/06/2025 10:19, Krzysztof Kozlowski wrote:
> > On Wed, Jun 11, 2025 at 03:53:15PM GMT, Inochi Amaoto wrote:
> >> Add bindings for the reset generator on the SOPHGO CV1800B
> >> RISC-V SoC.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> >> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> >> ---
> >> Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> >> index 1d1b84575960..bd8dfa998939 100644
> >> --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> >> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> >> @@ -17,6 +17,7 @@ properties:
> >> - sophgo,sg2044-reset
> >> - const: sophgo,sg2042-reset
> >> - const: sophgo,sg2042-reset
> >> + - const: sophgo,cv1800b-reset
> >
> > Keep alphabetical order. That's enum with previous entry, btw.
> >
>
> Heh, it was an enum when this was acked.
>
It seems that I have made a mistake when rebase. I will fix this in
the next version. Thanks for reminder.
Regards,
Inochi
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 8:19 ` Krzysztof Kozlowski
2025-06-11 8:21 ` Krzysztof Kozlowski
@ 2025-06-11 8:29 ` Inochi Amaoto
2025-06-11 9:09 ` Krzysztof Kozlowski
1 sibling, 1 reply; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 8:29 UTC (permalink / raw)
To: Krzysztof Kozlowski, Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille, Junhui Liu, devicetree, sophgo,
linux-kernel, linux-riscv, dmaengine, Yixun Lan, Longbin Li
On Wed, Jun 11, 2025 at 10:19:49AM +0200, Krzysztof Kozlowski wrote:
> On Wed, Jun 11, 2025 at 03:53:15PM GMT, Inochi Amaoto wrote:
> > Add bindings for the reset generator on the SOPHGO CV1800B
> > RISC-V SoC.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > Acked-by: Rob Herring (Arm) <robh@kernel.org>
> > ---
> > Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> > index 1d1b84575960..bd8dfa998939 100644
> > --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> > +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> > @@ -17,6 +17,7 @@ properties:
> > - sophgo,sg2044-reset
> > - const: sophgo,sg2042-reset
> > - const: sophgo,sg2042-reset
> > + - const: sophgo,cv1800b-reset
>
> Keep alphabetical order. That's enum with previous entry, btw.
>
There is a small question for this: should I move this before the entry
"const: sophgo,sg2042-reset", or before the first item entry?
Regards,
Inochi
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 8:29 ` Inochi Amaoto
@ 2025-06-11 9:09 ` Krzysztof Kozlowski
2025-06-11 9:45 ` Inochi Amaoto
0 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2025-06-11 9:09 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille, Junhui Liu, devicetree, sophgo,
linux-kernel, linux-riscv, dmaengine, Yixun Lan, Longbin Li
On 11/06/2025 10:29, Inochi Amaoto wrote:
> On Wed, Jun 11, 2025 at 10:19:49AM +0200, Krzysztof Kozlowski wrote:
>> On Wed, Jun 11, 2025 at 03:53:15PM GMT, Inochi Amaoto wrote:
>>> Add bindings for the reset generator on the SOPHGO CV1800B
>>> RISC-V SoC.
>>>
>>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
>>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
>>> ---
>>> Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
>>> index 1d1b84575960..bd8dfa998939 100644
>>> --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
>>> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
>>> @@ -17,6 +17,7 @@ properties:
>>> - sophgo,sg2044-reset
>>> - const: sophgo,sg2042-reset
>>> - const: sophgo,sg2042-reset
>>> + - const: sophgo,cv1800b-reset
>>
>> Keep alphabetical order. That's enum with previous entry, btw.
>>
>
> There is a small question for this: should I move this before the entry
> "const: sophgo,sg2042-reset", or before the first item entry?
It does not matter where you place the enum. There is no convention for
that.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-06-11 9:09 ` Krzysztof Kozlowski
@ 2025-06-11 9:45 ` Inochi Amaoto
0 siblings, 0 replies; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 9:45 UTC (permalink / raw)
To: Krzysztof Kozlowski, Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille, Junhui Liu, devicetree, sophgo,
linux-kernel, linux-riscv, dmaengine, Yixun Lan, Longbin Li
On Wed, Jun 11, 2025 at 11:09:50AM +0200, Krzysztof Kozlowski wrote:
> On 11/06/2025 10:29, Inochi Amaoto wrote:
> > On Wed, Jun 11, 2025 at 10:19:49AM +0200, Krzysztof Kozlowski wrote:
> >> On Wed, Jun 11, 2025 at 03:53:15PM GMT, Inochi Amaoto wrote:
> >>> Add bindings for the reset generator on the SOPHGO CV1800B
> >>> RISC-V SoC.
> >>>
> >>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> >>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> >>> ---
> >>> Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> >>> index 1d1b84575960..bd8dfa998939 100644
> >>> --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> >>> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> >>> @@ -17,6 +17,7 @@ properties:
> >>> - sophgo,sg2044-reset
> >>> - const: sophgo,sg2042-reset
> >>> - const: sophgo,sg2042-reset
> >>> + - const: sophgo,cv1800b-reset
> >>
> >> Keep alphabetical order. That's enum with previous entry, btw.
> >>
> >
> > There is a small question for this: should I move this before the entry
> > "const: sophgo,sg2042-reset", or before the first item entry?
> It does not matter where you place the enum. There is no convention for
> that.
>
Thanks. I will fix it
Regards,
Inochi
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 2/4] reset: simple: add support for Sophgo CV1800B
2025-06-11 7:53 [PATCH v3 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
2025-06-11 7:53 ` [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
@ 2025-06-11 7:53 ` Inochi Amaoto
2025-06-15 15:39 ` Alexander Sverdlin
2025-06-11 7:53 ` [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
2025-06-11 7:53 ` [PATCH v3 4/4] riscv: dts: sophgo: add reset configuration " Inochi Amaoto
3 siblings, 1 reply; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 7:53 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Vinod Koul, Alexander Sverdlin,
Yu Yuan, Ze Huang, Thomas Bonnefille
Cc: Junhui Liu, devicetree, sophgo, linux-kernel, linux-riscv,
dmaengine, Yixun Lan, Longbin Li
Reuse reset-simple driver for the Sophgo CV1800B reset generator.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
drivers/reset/reset-simple.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index 276067839830..79e94ecfe4f5 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "snps,dw-high-reset" },
{ .compatible = "snps,dw-low-reset",
.data = &reset_simple_active_low },
+ { .compatible = "sophgo,cv1800b-reset",
+ .data = &reset_simple_active_low },
{ .compatible = "sophgo,sg2042-reset",
.data = &reset_simple_active_low },
{ /* sentinel */ },
--
2.49.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 2/4] reset: simple: add support for Sophgo CV1800B
2025-06-11 7:53 ` [PATCH v3 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
@ 2025-06-15 15:39 ` Alexander Sverdlin
0 siblings, 0 replies; 14+ messages in thread
From: Alexander Sverdlin @ 2025-06-15 15:39 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Yu Yuan, Ze Huang, Thomas Bonnefille
Cc: Junhui Liu, devicetree, sophgo, linux-kernel, linux-riscv,
dmaengine, Yixun Lan, Longbin Li
Thanks for the patch, Inochi!
On Wed, 2025-06-11 at 15:53 +0800, Inochi Amaoto wrote:
> Reuse reset-simple driver for the Sophgo CV1800B reset generator.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Successfully tested with USB series in host mode on Milk-V Duo Module 01 EVB:
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
> drivers/reset/reset-simple.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
> index 276067839830..79e94ecfe4f5 100644
> --- a/drivers/reset/reset-simple.c
> +++ b/drivers/reset/reset-simple.c
> @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
> { .compatible = "snps,dw-high-reset" },
> { .compatible = "snps,dw-low-reset",
> .data = &reset_simple_active_low },
> + { .compatible = "sophgo,cv1800b-reset",
> + .data = &reset_simple_active_low },
> { .compatible = "sophgo,sg2042-reset",
> .data = &reset_simple_active_low },
> { /* sentinel */ },
--
Alexander Sverdlin.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-06-11 7:53 [PATCH v3 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
2025-06-11 7:53 ` [PATCH v3 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
2025-06-11 7:53 ` [PATCH v3 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
@ 2025-06-11 7:53 ` Inochi Amaoto
2025-06-11 10:07 ` Junhui Liu
2025-06-15 15:39 ` Alexander Sverdlin
2025-06-11 7:53 ` [PATCH v3 4/4] riscv: dts: sophgo: add reset configuration " Inochi Amaoto
3 siblings, 2 replies; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 7:53 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Vinod Koul, Alexander Sverdlin,
Yu Yuan, Ze Huang, Thomas Bonnefille
Cc: Junhui Liu, devicetree, sophgo, linux-kernel, linux-riscv,
dmaengine, Yixun Lan, Longbin Li
Add reset generator node for all CV18XX series SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv180x.dtsi | 7 ++
arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
2 files changed, 105 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index ed06c3609fb2..4c3d16764131 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/sophgo,cv1800.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx-reset.h"
/ {
#address-cells = <1>;
@@ -24,6 +25,12 @@ soc {
#size-cells = <1>;
ranges;
+ rst: reset-controller@3003000 {
+ compatible = "sophgo,cv1800b-reset";
+ reg = <0x3003000 0x1000>;
+ #reset-cells = <1>;
+ };
+
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
new file mode 100644
index 000000000000..7e7c5ca2dbbd
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#ifndef _SOPHGO_CV18XX_RESET
+#define _SOPHGO_CV18XX_RESET
+
+#define RST_DDR 2
+#define RST_H264C 3
+#define RST_JPEG 4
+#define RST_H265C 5
+#define RST_VIPSYS 6
+#define RST_TDMA 7
+#define RST_TPU 8
+#define RST_TPUSYS 9
+#define RST_USB 11
+#define RST_ETH0 12
+#define RST_ETH1 13
+#define RST_NAND 14
+#define RST_EMMC 15
+#define RST_SD0 16
+#define RST_SDMA 18
+#define RST_I2S0 19
+#define RST_I2S1 20
+#define RST_I2S2 21
+#define RST_I2S3 22
+#define RST_UART0 23
+#define RST_UART1 24
+#define RST_UART2 25
+#define RST_UART3 26
+#define RST_I2C0 27
+#define RST_I2C1 28
+#define RST_I2C2 29
+#define RST_I2C3 30
+#define RST_I2C4 31
+#define RST_PWM0 32
+#define RST_PWM1 33
+#define RST_PWM2 34
+#define RST_PWM3 35
+#define RST_SPI0 40
+#define RST_SPI1 41
+#define RST_SPI2 42
+#define RST_SPI3 43
+#define RST_GPIO0 44
+#define RST_GPIO1 45
+#define RST_GPIO2 46
+#define RST_EFUSE 47
+#define RST_WDT 48
+#define RST_AHB_ROM 49
+#define RST_SPIC 50
+#define RST_TEMPSEN 51
+#define RST_SARADC 52
+#define RST_COMBO_PHY0 58
+#define RST_SPI_NAND 61
+#define RST_SE 62
+#define RST_UART4 74
+#define RST_GPIO3 75
+#define RST_SYSTEM 76
+#define RST_TIMER 77
+#define RST_TIMER0 78
+#define RST_TIMER1 79
+#define RST_TIMER2 80
+#define RST_TIMER3 81
+#define RST_TIMER4 82
+#define RST_TIMER5 83
+#define RST_TIMER6 84
+#define RST_TIMER7 85
+#define RST_WGN0 86
+#define RST_WGN1 87
+#define RST_WGN2 88
+#define RST_KEYSCAN 89
+#define RST_AUDDAC 91
+#define RST_AUDDAC_APB 92
+#define RST_AUDADC 93
+#define RST_VCSYS 95
+#define RST_ETHPHY 96
+#define RST_ETHPHY_APB 97
+#define RST_AUDSRC 98
+#define RST_VIP_CAM0 99
+#define RST_WDT1 100
+#define RST_WDT2 101
+#define RST_AUTOCLEAR_CPUCORE0 256
+#define RST_AUTOCLEAR_CPUCORE1 257
+#define RST_AUTOCLEAR_CPUCORE2 258
+#define RST_AUTOCLEAR_CPUCORE3 259
+#define RST_AUTOCLEAR_CPUSYS0 260
+#define RST_AUTOCLEAR_CPUSYS1 261
+#define RST_AUTOCLEAR_CPUSYS2 262
+#define RST_CPUCORE0 288
+#define RST_CPUCORE1 289
+#define RST_CPUCORE2 290
+#define RST_CPUCORE3 291
+#define RST_CPUSYS0 292
+#define RST_CPUSYS1 293
+#define RST_CPUSYS2 294
+
+#endif /* _SOPHGO_CV18XX_RESET */
--
2.49.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-06-11 7:53 ` [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
@ 2025-06-11 10:07 ` Junhui Liu
2025-06-15 15:39 ` Alexander Sverdlin
1 sibling, 0 replies; 14+ messages in thread
From: Junhui Liu @ 2025-06-11 10:07 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Alexander Sverdlin, Yu Yuan,
Ze Huang, Thomas Bonnefille
Cc: devicetree, sophgo, linux-kernel, linux-riscv, dmaengine,
Yixun Lan, Longbin Li
On 2025/6/11 15:53, Inochi Amaoto wrote:
> Add reset generator node for all CV18XX series SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Test RST_CPUSYS2 ok with the C906L remoteproc driver. Thanks!
Tested-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> arch/riscv/boot/dts/sophgo/cv180x.dtsi | 7 ++
> arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
> 2 files changed, 105 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index ed06c3609fb2..4c3d16764131 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/clock/sophgo,cv1800.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv18xx-reset.h"
>
> / {
> #address-cells = <1>;
> @@ -24,6 +25,12 @@ soc {
> #size-cells = <1>;
> ranges;
>
> + rst: reset-controller@3003000 {
> + compatible = "sophgo,cv1800b-reset";
> + reg = <0x3003000 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> gpio0: gpio@3020000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0x3020000 0x1000>;
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> new file mode 100644
> index 000000000000..7e7c5ca2dbbd
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#ifndef _SOPHGO_CV18XX_RESET
> +#define _SOPHGO_CV18XX_RESET
> +
> +#define RST_DDR 2
> +#define RST_H264C 3
> +#define RST_JPEG 4
> +#define RST_H265C 5
> +#define RST_VIPSYS 6
> +#define RST_TDMA 7
> +#define RST_TPU 8
> +#define RST_TPUSYS 9
> +#define RST_USB 11
> +#define RST_ETH0 12
> +#define RST_ETH1 13
> +#define RST_NAND 14
> +#define RST_EMMC 15
> +#define RST_SD0 16
> +#define RST_SDMA 18
> +#define RST_I2S0 19
> +#define RST_I2S1 20
> +#define RST_I2S2 21
> +#define RST_I2S3 22
> +#define RST_UART0 23
> +#define RST_UART1 24
> +#define RST_UART2 25
> +#define RST_UART3 26
> +#define RST_I2C0 27
> +#define RST_I2C1 28
> +#define RST_I2C2 29
> +#define RST_I2C3 30
> +#define RST_I2C4 31
> +#define RST_PWM0 32
> +#define RST_PWM1 33
> +#define RST_PWM2 34
> +#define RST_PWM3 35
> +#define RST_SPI0 40
> +#define RST_SPI1 41
> +#define RST_SPI2 42
> +#define RST_SPI3 43
> +#define RST_GPIO0 44
> +#define RST_GPIO1 45
> +#define RST_GPIO2 46
> +#define RST_EFUSE 47
> +#define RST_WDT 48
> +#define RST_AHB_ROM 49
> +#define RST_SPIC 50
> +#define RST_TEMPSEN 51
> +#define RST_SARADC 52
> +#define RST_COMBO_PHY0 58
> +#define RST_SPI_NAND 61
> +#define RST_SE 62
> +#define RST_UART4 74
> +#define RST_GPIO3 75
> +#define RST_SYSTEM 76
> +#define RST_TIMER 77
> +#define RST_TIMER0 78
> +#define RST_TIMER1 79
> +#define RST_TIMER2 80
> +#define RST_TIMER3 81
> +#define RST_TIMER4 82
> +#define RST_TIMER5 83
> +#define RST_TIMER6 84
> +#define RST_TIMER7 85
> +#define RST_WGN0 86
> +#define RST_WGN1 87
> +#define RST_WGN2 88
> +#define RST_KEYSCAN 89
> +#define RST_AUDDAC 91
> +#define RST_AUDDAC_APB 92
> +#define RST_AUDADC 93
> +#define RST_VCSYS 95
> +#define RST_ETHPHY 96
> +#define RST_ETHPHY_APB 97
> +#define RST_AUDSRC 98
> +#define RST_VIP_CAM0 99
> +#define RST_WDT1 100
> +#define RST_WDT2 101
> +#define RST_AUTOCLEAR_CPUCORE0 256
> +#define RST_AUTOCLEAR_CPUCORE1 257
> +#define RST_AUTOCLEAR_CPUCORE2 258
> +#define RST_AUTOCLEAR_CPUCORE3 259
> +#define RST_AUTOCLEAR_CPUSYS0 260
> +#define RST_AUTOCLEAR_CPUSYS1 261
> +#define RST_AUTOCLEAR_CPUSYS2 262
> +#define RST_CPUCORE0 288
> +#define RST_CPUCORE1 289
> +#define RST_CPUCORE2 290
> +#define RST_CPUCORE3 291
> +#define RST_CPUSYS0 292
> +#define RST_CPUSYS1 293
> +#define RST_CPUSYS2 294
> +
> +#endif /* _SOPHGO_CV18XX_RESET */
--
Best regards,
Junhui Liu
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-06-11 7:53 ` [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
2025-06-11 10:07 ` Junhui Liu
@ 2025-06-15 15:39 ` Alexander Sverdlin
1 sibling, 0 replies; 14+ messages in thread
From: Alexander Sverdlin @ 2025-06-15 15:39 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Vinod Koul, Yu Yuan, Ze Huang, Thomas Bonnefille
Cc: Junhui Liu, devicetree, sophgo, linux-kernel, linux-riscv,
dmaengine, Yixun Lan, Longbin Li
Thanks for the patch, Inochi!
On Wed, 2025-06-11 at 15:53 +0800, Inochi Amaoto wrote:
> Add reset generator node for all CV18XX series SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Successfully tested with USB series in host mode on Milk-V Duo Module 01 EVB:
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/cv180x.dtsi | 7 ++
> arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
> 2 files changed, 105 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
--
Alexander Sverdlin.
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
2025-06-11 7:53 [PATCH v3 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
` (2 preceding siblings ...)
2025-06-11 7:53 ` [PATCH v3 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
@ 2025-06-11 7:53 ` Inochi Amaoto
3 siblings, 0 replies; 14+ messages in thread
From: Inochi Amaoto @ 2025-06-11 7:53 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Vinod Koul, Alexander Sverdlin,
Yu Yuan, Ze Huang, Thomas Bonnefille
Cc: Junhui Liu, devicetree, sophgo, linux-kernel, linux-riscv,
dmaengine, Yixun Lan, Longbin Li
Add known reset configuration for existed device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index 4c3d16764131..e91bb512b099 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -36,6 +36,7 @@ gpio0: gpio@3020000 {
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -54,6 +55,7 @@ gpio1: gpio@3021000 {
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO1>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -72,6 +74,7 @@ gpio2: gpio@3022000 {
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO2>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -90,6 +93,7 @@ gpio3: gpio@3023000 {
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO3>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -133,6 +137,7 @@ i2c0: i2c@4000000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C0>;
status = "disabled";
};
@@ -144,6 +149,7 @@ i2c1: i2c@4010000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C1>;
status = "disabled";
};
@@ -155,6 +161,7 @@ i2c2: i2c@4020000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C2>;
status = "disabled";
};
@@ -166,6 +173,7 @@ i2c3: i2c@4030000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C3>;
status = "disabled";
};
@@ -177,6 +185,7 @@ i2c4: i2c@4040000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C4>;
status = "disabled";
};
@@ -188,6 +197,7 @@ uart0: serial@4140000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART0>;
status = "disabled";
};
@@ -199,6 +209,7 @@ uart1: serial@4150000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART1>;
status = "disabled";
};
@@ -210,6 +221,7 @@ uart2: serial@4160000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART2>;
status = "disabled";
};
@@ -221,6 +233,7 @@ uart3: serial@4170000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART3>;
status = "disabled";
};
@@ -232,6 +245,7 @@ spi0: spi@4180000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI0>;
status = "disabled";
};
@@ -243,6 +257,7 @@ spi1: spi@4190000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI1>;
status = "disabled";
};
@@ -254,6 +269,7 @@ spi2: spi@41a0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI2>;
status = "disabled";
};
@@ -265,6 +281,7 @@ spi3: spi@41b0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI3>;
status = "disabled";
};
@@ -276,6 +293,7 @@ uart4: serial@41c0000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART4>;
status = "disabled";
};
--
2.49.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread