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From: Xi Ruoyao <xry111@linuxfromscratch.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	 linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Thu, 27 Jul 2023 17:18:51 +0800	[thread overview]
Message-ID: <c5e44ec519f4d56a71d416cf43a375cdbf0b9358.camel@linuxfromscratch.org> (raw)
In-Reply-To: <4986b92f1a5aa303a529c6004aaedd2184c3ccf7.camel@linuxfromscratch.org>

On Thu, 2023-07-27 at 08:54 +0800, Xi Ruoyao wrote:
> On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote:
> > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote:
> > > which dts r u using? see below.
> > > 
> > > > 
> > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) can
> > > > miscompile the kernel?
> > 
> > /* snip */
> > 
> > > > Boot HART ID              : 0
> > > > Boot HART Domain          : root
> > > > Boot HART Priv Version    : v1.11
> > > > Boot HART Base ISA        : rv64imafdcvx
> > > 
> > > what? I don't think the mainline dts provide v and x. 
> > 
> > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb
> > into /boot and loaded it with u-boot "load" command onto 0x46000000, and
> > passed this address to the booti command.
> > 
> > But maybe I've copied the wrong file or made some other mistake... I'll
> > recheck.
> 
> Hmm, and if I read OpenSBI code correctly, this line reflects the
> content of the misa CSR, not the DT riscv,isa value.
> 
> The log of successful boot provided by Drew also contains
> "rv64imafdcvx":
> 
> https://gist.github.com/pdp7/23259595a7570f1f11086d286e16dfb6

I tried a __show_reg call before the panic:

[    0.012953] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.5.0-rc3 #7
[    0.012967] Hardware name: Sipeed Lichee Pi 4A (DT)
[    0.012976] epc : ffffffff80c84a60 ra : 0000000000000000 sp : ffffffff8004dfee
[    0.012988]  gp : 0000000200000120 tp : ffffffff80c03d20 t0 : ffffffff80002d6c
[    0.012997]  t1 : ffffffff8004dfee t2 : ffffffff8004dfe6 s0 : ffffffff80c03d20
[    0.013005]  s1 : ffffffff80c966f0 a0 : ffffffff80c98140 a1 : 2000000000000000
[    0.013012]  a2 : 0000000000000043 a3 : 203a656c6f736e6f a4 : ffffffff80c03def
[    0.013021]  a5 : ffffffff80dcb4a0 a6 : 0000000000000001 a7 : 0000000000000014
[    0.013030]  s2 : 000000000000000a s3 : 0000000000000000 s4 : 0000000000000000
[    0.013036]  s5 : ffffffd9fef69740 s6 : 0000000000000008 s7 : 0000000000000032
[    0.013046]  s8 : 0000000000000002 s9 : ffffffff80c03df0 s10: ffffffff80dcb4e8
[    0.013056]  s11: ffffffff80dc7c80 t3 : ffffffff80c03d48 t4 : ffffffff80dcb2f0
[    0.013064]  t5 : ffffffff80c84a60 t6 : ffffffff80c10b98
[    0.013071] status: 0000000000000000 badaddr: 0000000000000001 cause: ffffffff80dcb4f7
[    0.013082] Kernel panic - not syncing: unexpected interrupt cause

I compared these with System.map and the result seems completely erratic
(for example, sp is out of init_stack, and gp is not __global_pointer$).


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  reply	other threads:[~2023-07-27  9:19 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley
2023-06-18 16:14   ` Jisheng Zhang
2023-06-17 18:20 ` Conor Dooley
2023-06-18 16:25   ` Jisheng Zhang
2023-06-18 21:01     ` Conor Dooley
2023-06-20 22:52     ` Conor Dooley
2023-06-20 22:55       ` Conor Dooley
2023-07-25  7:38 ` Xi Ruoyao
2023-07-25  7:52   ` Conor Dooley
2023-07-25  8:10     ` Conor Dooley
2023-07-25 14:32       ` Drew Fustini
2023-07-25  8:26     ` Xi Ruoyao
2023-07-25 14:58     ` Jisheng Zhang
2023-07-26 12:48       ` Xi Ruoyao
2023-07-26 15:00         ` Jisheng Zhang
2023-07-27  0:14           ` Xi Ruoyao
2023-07-27  0:54             ` Xi Ruoyao
2023-07-27  9:18               ` Xi Ruoyao [this message]
2023-07-27 16:11               ` Jisheng Zhang
2023-07-27 16:29                 ` Xi Ruoyao
2023-07-28  7:04                   ` Drew Fustini
2023-07-28  7:40                     ` Xi Ruoyao
2023-07-28 10:05                       ` Xi Ruoyao
2023-07-28 10:23                         ` Emil Renner Berthing
2023-07-28 17:53                           ` Drew Fustini
2023-07-29  7:11                             ` Xi Ruoyao
2023-07-28  0:11               ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:46   ` Conor Dooley

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