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Sat, 08 Aug 2026 06:07:23 -0700 (PDT) Received: from localhost ([2403:2c80:17:1e::20db]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3925fc6c13asm6117441a91.2.2026.08.08.06.07.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Aug 2026 06:07:22 -0700 (PDT) Date: Sat, 08 Aug 2026 21:07:20 +0800 Message-ID: From: Cody Kang To: Philipp Zabel Cc: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org Subject: Re: [PATCH RESEND 08/17] drm/spacemit: add Saturn DPU core types, cmdlist and display MMU In-Reply-To: <3d4204dbd1c73d50193144d1944d8237c625f6e3.camel@pengutronix.de> References: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> <20260725-k3-display-v1-8-6de34d80e86c@gmail.com> <3d4204dbd1c73d50193144d1944d8237c625f6e3.camel@pengutronix.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260808_060724_742634_CDC21F9D X-CRM114-Status: GOOD ( 18.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 27 Jul 2026 09:35:35 +0200, Philipp Zabel wrote: > On Sa, 2026-07-25 at 00:51 -0400, Cody Kang via B4 Relay wrote: > > From: Cody Kang > > > > Register programming of the Saturn DPU is batched: the driver builds > > per-module register lists in memory and the hardware command-list > > engine replays them at frame boundaries, while scanout buffers are > > mapped through the DPU's private address translation unit (DMMU) > > rather than scanned out by physical address. > > > > Add the shared driver types, the MMIO field accessors, the trace > > events, the command-list builder and the DMMU table code. Some DPU > > configuration registers are write-only, so a read-modify-write would > > corrupt neighbouring fields; byte- and halfword-aligned fields are > > therefore written at their native width instead. > > > > Signed-off-by: Cody Kang > > --- > > drivers/gpu/drm/spacemit/dpu/dpu_saturn.h | 35 +++ > > drivers/gpu/drm/spacemit/dpu/dpu_trace.h | 350 ++++++++++++++++++++++++++++ > > drivers/gpu/drm/spacemit/spacemit_cmdlist.c | 304 ++++++++++++++++++++++++ > > drivers/gpu/drm/spacemit/spacemit_cmdlist.h | 146 ++++++++++++ > > drivers/gpu/drm/spacemit/spacemit_crtc.h | 259 ++++++++++++++++++++ > > drivers/gpu/drm/spacemit/spacemit_dmmu.c | 103 ++++++++ > > drivers/gpu/drm/spacemit/spacemit_dmmu.h | 40 ++++ > > drivers/gpu/drm/spacemit/spacemit_dpu_reg.h | 108 +++++++++ > > drivers/gpu/drm/spacemit/spacemit_drm.h | 68 ++++++ > > 9 files changed, 1413 insertions(+) > > > [...] > > diff --git a/drivers/gpu/drm/spacemit/spacemit_cmdlist.h b/drivers/gpu/drm/spacemit/spacemit_cmdlist.h > > new file mode 100644 > > index 000000000000..d5acdbeb3b0e > > --- /dev/null > > +++ b/drivers/gpu/drm/spacemit/spacemit_cmdlist.h > > @@ -0,0 +1,146 @@ > [...] > > +struct spacemit_crtc { > > + struct device *dev; > > + struct drm_crtc crtc; > > + const struct dpu_core_ops *core; > > + struct dpu_mmu_tbl mmu_tbl; > > + int dev_id; > > + int irq_online; > > + struct timer_list cfg_rdy_timer; > > + > > + bool is_1st_f; > > + bool first_modeset; > > + struct dpu_clk_context clk_ctx; > > + u32 aclk; > > + u32 out_format; > > + > > + struct reset_control *mclk_reset; > > + struct reset_control *lcd_reset; > > + struct reset_control *esc_reset; > > + struct reset_control *aclk_reset; > > + struct reset_control *dsc_reset; > > Why are these duplicated from spacemit_drm_private? > dpu_pm_suspend/resume() in patch 10 have access to priv. You are right, they are plain 1:1 copies. Will drop the five pointers from struct spacemit_crtc in v2; the reset sequencing in spacemit_crtc.c and the suspend/resume paths will take them from spacemit_drm_private instead. Thanks for the review. Cody _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv