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Fri, 21 Jul 2023 01:35:01 -0700 (PDT) Received: from [192.168.1.20] ([178.197.223.104]) by smtp.gmail.com with ESMTPSA id x2-20020adff642000000b0031444673643sm3512256wrp.57.2023.07.21.01.34.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Jul 2023 01:35:00 -0700 (PDT) Message-ID: Date: Fri, 21 Jul 2023 10:34:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, will@kernel.org, mark.rutland@arm.com, tglx@linutronix.de, peterz@infradead.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: zong.li@sifive.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Nick Hu References: <20230720135125.21240-1-eric.lin@sifive.com> <20230720135125.21240-2-eric.lin@sifive.com> From: Krzysztof Kozlowski In-Reply-To: <20230720135125.21240-2-eric.lin@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_013503_708919_8F100675 X-CRM114-Status: GOOD ( 11.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 20/07/2023 15:51, Eric Lin wrote: > This add YAML DT binding documentation for SiFive Private L2 > cache controller > > Signed-off-by: Eric Lin > Reviewed-by: Zong Li > Reviewed-by: Nick Hu ... > +properties: > + compatible: > + items: > + - const: sifive,pl2cache1 I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC." If not part of any SoC, then where is it? Why are you adding it to the kernel? > + - const: cache > + > + cache-block-size: true > + cache-level: true > + cache-sets: true > + cache-size: true > + cache-unified: true > + > + reg: > + maxItems: 1 > + > + next-level-cache: true > + > +required: > + - compatible > + - cache-block-size > + - cache-level > + - cache-sets > + - cache-size > + - cache-unified > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + cache-controller@10104000 { > + compatible = "sifive,pl2cache1","cache"; Missing space. > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <512>; > + cache-size = <262144>; > + cache-unified; > + reg = <0x10104000 0x4000>; reg is after compatible. > + next-level-cache = <&L4>; > + }; Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv