From: John Garry <john.garry@huawei.com>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: "Genevieve Chan" <genevieve.chan@starfivetech.com>,
"João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>,
"Nikita Shubin" <n.shubin@yadro.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
"Atish Patra" <atishp@atishpatra.org>
Subject: Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile
Date: Wed, 8 Jun 2022 16:51:14 +0100 [thread overview]
Message-ID: <cf544be3-5c83-044d-95a7-62dd3695a3cc@huawei.com> (raw)
In-Reply-To: <20220608174107.7b94e545@redslave.neermore.group>
On 08/06/2022 15:41, Nikita Shubin wrote:
>>> mat:
>>> +# MIDR,Version,JSON/file/pathname,Type
>>> +#
>>> +# where
>>> +# MIDR Processor version
>> ARM, no?
I'm just saying that MIDR is for ARM, so please ensure that this term is
correct for riscv
> I've messed with --cc-cmd badly and didn't include every one in cover
> letter, sorry for that, attaching link to cover letter:
>
> https://lore.kernel.org/all/20220607131648.29439-1-nikita.shubin@maquefel.me/
>
> They are ARM inspired indeed.
>
>
>>> +# Variant[23:20] and Revision [3:0] should be zero.
>>> +# Version could be used to track version of JSON file
>>> +# but currently unused.
>>> +# JSON/file/pathname is the path to JSON file, relative
>>> +# to tools/perf/pmu-events/arch/riscv/.
>>> +# Type is core, uncore etc
>>> +#
>>> +#
>>> +#Family-model,Version,Filename,EventType
>>> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json
>>> b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode
>>> 100644 index 000000000000..013e50efad99
>>> --- /dev/null
>>> +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
>> where or how are these referenced?
> Currently they are not referenced in this version of series at all,
ok, right, so a general kernel policy is not to include code which is
not referenced.
> their purpose is to be used like "ArchStdEvent".
>
> Through any RISCV implementation should have at least these 3 events.
Thanks,
John
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next prev parent reply other threads:[~2022-06-08 15:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-07 13:16 [PATCH v3 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2022-06-07 13:16 ` [PATCH v3 1/4] RISC-V: Create unique identification for SoC PMU Nikita Shubin
2022-06-07 16:37 ` Atish Patra
2022-06-08 8:47 ` Nikita Shubin
2022-06-14 10:16 ` Sunil V L
2022-06-07 13:16 ` [PATCH v3 2/4] RISC-V: Support CPUID for risc-v in perf Nikita Shubin
2022-06-09 13:54 ` Will Deacon
2022-06-07 13:16 ` [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile Nikita Shubin
2022-06-08 10:45 ` John Garry
2022-06-08 14:41 ` Nikita Shubin
2022-06-08 15:51 ` John Garry [this message]
2022-06-07 13:16 ` [PATCH v3 4/4] RISC-V: Added HiFive Unmatched PMU events Nikita Shubin
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