From: "Clément Léger" <cleger@rivosinc.com>
To: Himanshu Chauhan <hchauhan@ventanamicro.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: apatel@ventanamicro.com, tony.luck@intel.com,
robert.moore@intel.com, conor@kernel.org, james.morse@arm.com,
paul.walmsley@sifive.com, palmer@dabbelt.com, ardb@kernel.org,
lenb@kernel.org
Subject: Re: [RFC PATCH v1 02/10] riscv: Define arch_apei_get_mem_attribute for RISC-V
Date: Thu, 27 Feb 2025 13:57:31 +0100 [thread overview]
Message-ID: <cf568ee0-8baf-4701-9e22-0b71792cf329@rivosinc.com> (raw)
In-Reply-To: <20250227123628.2931490-3-hchauhan@ventanamicro.com>
On 27/02/2025 13:36, Himanshu Chauhan wrote:
> ghes_map function uses arch_apei_get_mem_attribute to get the
> protection bits for a given physical address. These protection
> bits are then used to map the physical address.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> ---
> arch/riscv/include/asm/acpi.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
> index 6e13695120bc..0c599452ef48 100644
> --- a/arch/riscv/include/asm/acpi.h
> +++ b/arch/riscv/include/asm/acpi.h
> @@ -27,6 +27,26 @@ extern int acpi_disabled;
> extern int acpi_noirq;
> extern int acpi_pci_disabled;
>
> +#ifdef CONFIG_ACPI_APEI
> +/*
> + * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling
> + * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode
> + * with a kernel command line parameter "acpi=nocmcoff". But we don't
> + * have this IA-32 specific feature on ARM64, this definition is only
Hi Himanshu
s/ARM/RISC-V
Thanks,
Clément
> + * for compatibility.
> + */
> +#define acpi_disable_cmcff 1
> +static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr)
> +{
> + /*
> + * Until we have a way to look for EFI memory attributes.
> + */
> + return PAGE_KERNEL;
> +}
> +#else /* CONFIG_ACPI_APEI */
> +#define acpi_disable_cmcff 0
> +#endif /* !CONFIG_ACPI_APEI */
> +
> static inline void disable_acpi(void)
> {
> acpi_disabled = 1;
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next prev parent reply other threads:[~2025-02-27 14:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 12:36 [RFC PATCH v1 00/10] Add RAS support for RISC-V architecture Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 01/10] riscv: Define ioremap_cache for RISC-V Himanshu Chauhan
2025-05-05 12:32 ` Anup Patel
2025-02-27 12:36 ` [RFC PATCH v1 02/10] riscv: Define arch_apei_get_mem_attribute " Himanshu Chauhan
2025-02-27 12:57 ` Clément Léger [this message]
2025-02-27 12:36 ` [RFC PATCH v1 03/10] acpi: Introduce SSE in HEST notification types Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 05/10] riscv: conditionally compile GHES NMI spool function Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 06/10] riscv: Add functions to register ghes having SSE notification Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 07/10] riscv: Add RISC-V entries in processor type and ISA strings Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 08/10] riscv: Introduce HEST SSE notification handlers Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 09/10] riscv: Add config option to enable APEI SSE handler Himanshu Chauhan
2025-02-27 12:36 ` [RFC PATCH v1 10/10] riscv: Enable APEI and NMI safe cmpxchg options required for RAS Himanshu Chauhan
2025-09-12 7:30 ` [RFC PATCH v1 00/10] Add RAS support for RISC-V architecture Ruidong Tian
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