From: <Conor.Dooley@microchip.com>
To: <zong.li@sifive.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<greentime.hu@sifive.com>, <ben.dooks@sifive.com>, <bp@alien8.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts
Date: Mon, 5 Sep 2022 18:14:49 +0000 [thread overview]
Message-ID: <cf98f606-a392-37e9-be92-cb854afb4951@microchip.com> (raw)
In-Reply-To: <20220905083125.29426-4-zong.li@sifive.com>
On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Composable cache could be L2 or L3 cache, use 'cache-level' property of
> device node to determine the level.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
> drivers/soc/sifive/sifive_ccache.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 1b16a196547f..0e0eb85c94d8 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -38,6 +38,7 @@
> static void __iomem *ccache_base;
> static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> static struct riscv_cacheinfo_ops ccache_cache_ops;
> +static int level;
Can you have a system with a composable l2 & l3 cache?
>
> enum {
> DIR_CORR = 0,
> @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
> static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
> {
> /* We want to use private group for composable cache only */
> - if (this_leaf->level == 2)
> + if (this_leaf->level == level)
> return &priv_attr_group;
> else
> return NULL;
> @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
> if (!ccache_base)
> return -ENOMEM;
>
> + if (of_property_read_u32(np, "cache-level", &level))
> + return -ENODEV;
> +
> intr_num = of_property_count_u32_elems(np, "interrupts");
> if (!intr_num) {
> pr_err("CCACHE: no interrupts property\n");
> --
> 2.17.1
>
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next prev parent reply other threads:[~2022-09-05 19:15 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 8:31 [PATCH v2 0/6] Use composable cache instead of L2 cache Zong Li
2022-09-05 8:31 ` [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-05 18:02 ` Conor.Dooley
2022-09-08 21:21 ` Rob Herring
2022-09-08 21:32 ` Conor.Dooley
2022-09-05 8:31 ` [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive " Zong Li
2022-09-05 18:10 ` Conor.Dooley
2022-09-06 1:52 ` Zong Li
2022-09-05 18:46 ` Conor.Dooley
2022-09-06 1:44 ` Zong Li
2022-09-06 6:23 ` Conor.Dooley
2022-09-06 6:51 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-05 18:14 ` Conor.Dooley [this message]
2022-09-06 1:57 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-05 18:36 ` Conor.Dooley
2022-09-06 1:40 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-05 18:44 ` Conor.Dooley
2022-09-06 1:38 ` Zong Li
2022-09-05 8:31 ` [PATCH v2 6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
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