From: Gary Guo <gary@garyguo.net>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Anup Patel <anup.patel@wdc.com>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>, Gary Guo <gary@garyguo.net>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: [PATCH v2 0/4] Improvements related to TLB and I$ flush
Date: Fri, 8 Mar 2019 18:40:40 +0000 [thread overview]
Message-ID: <cover.1552069700.git.gary@garyguo.net> (raw)
From: Gary Guo <gary@garyguo.net>
Here's the revised version of my TLB/I$ flush improvement. Originally the
I$ part is a separate patch but I've decided to put into the same patch
series as they're somewhat related.
Instead of using Kconfig, the code now adds two kernel boot parameters
instead, tlbi_max_ops=<int> and tlbi_method=<ipi|sbi>.
Gary Guo (4):
riscv: move flush_icache_{all,mm} to cacheflush.c
riscv: move switch_mm to its own file
riscv: fix sbi_remote_sfence_vma{,_asid}.
riscv: rewrite tlb flush for performance
arch/riscv/include/asm/cacheflush.h | 2 +-
arch/riscv/include/asm/mmu_context.h | 59 +-------
arch/riscv/include/asm/pgtable.h | 2 +-
arch/riscv/include/asm/sbi.h | 19 ++-
arch/riscv/include/asm/tlbflush.h | 73 ++++-----
arch/riscv/kernel/smp.c | 49 ------
arch/riscv/mm/Makefile | 2 +
arch/riscv/mm/cacheflush.c | 61 ++++++++
arch/riscv/mm/context.c | 77 ++++++++++
arch/riscv/mm/tlbflush.c | 216 +++++++++++++++++++++++++++
10 files changed, 399 insertions(+), 161 deletions(-)
create mode 100644 arch/riscv/mm/context.c
create mode 100644 arch/riscv/mm/tlbflush.c
--
2.17.1
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next reply other threads:[~2019-03-08 18:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-08 18:40 Gary Guo [this message]
2019-03-08 18:40 ` [PATCH v2 1/4] riscv: move flush_icache_{all,mm} to cacheflush.c Gary Guo
2019-03-08 18:40 ` [PATCH v2 3/4] riscv: fix sbi_remote_sfence_vma{,_asid} Gary Guo
2019-03-08 18:40 ` [PATCH v2 2/4] riscv: move switch_mm to its own file Gary Guo
2019-03-08 18:40 ` [PATCH v2 4/4] riscv: rewrite tlb flush for performance Gary Guo
2019-03-09 2:22 ` Gary Guo
2019-03-09 8:17 ` Atish Patra
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