From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
linux-riscv@lists.infradead.org
Subject: [PATCH 0/2] RISC-V: minor fixes to the QEMU workaround in ISA string parser
Date: Sat, 22 Jul 2023 06:22:36 +0000 [thread overview]
Message-ID: <cover.1690006695.git.research_trasio@irq.a4lg.com> (raw)
Although hardly functional (mostly editorial), the author hopes this to be
useful to give less confusion to kernel developers and improve
the maintainability of the RISC-V ISA parser, including the QEMU-related
workaround that is "fixed" by this patch set (intended for QEMU < v7.1).
v1:
(the initial submission; see the each PATCH for details)
Tsukasa OI (2):
RISC-V: make ISA string workaround case-insensitive
RISC-V: fix the comment for ISA string workaround
arch/riscv/kernel/cpufeature.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
--
2.40.0
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next reply other threads:[~2023-07-22 6:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-22 6:22 Tsukasa OI [this message]
2023-07-22 6:22 ` [PATCH 1/2] RISC-V: make ISA string workaround case-insensitive Tsukasa OI
2023-07-22 10:49 ` Conor Dooley
2023-07-22 6:22 ` [PATCH 2/2] RISC-V: fix the comment for ISA string workaround Tsukasa OI
2023-07-22 10:52 ` Conor Dooley
2023-07-22 11:22 ` Tsukasa OI
2023-07-22 11:28 ` Conor Dooley
2023-07-26 5:44 ` [PATCH v2 0/1] RISC-V: clarification of the QEMU workaround in the ISA parser Tsukasa OI
2023-07-26 5:44 ` [PATCH v2 1/1] RISC-V: clarify the QEMU workaround in " Tsukasa OI
2023-07-26 6:56 ` Conor Dooley
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