[PATCH 0/2] RISC-V: minor fixes to the QEMU workaround in ISA string parser

[PATCH 0/2] RISC-V: minor fixes to the QEMU workaround in ISA string parser

[Tsukasa OI]

Although hardly functional (mostly editorial), the author hopes this to be
useful to give less confusion to kernel developers and improve
the maintainability of the RISC-V ISA parser, including the QEMU-related
workaround that is "fixed" by this patch set (intended for QEMU < v7.1).

v1:
(the initial submission; see the each PATCH for details)




Tsukasa OI (2):
  RISC-V: make ISA string workaround case-insensitive
  RISC-V: fix the comment for ISA string workaround

 arch/riscv/kernel/cpufeature.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

-- 
2.40.0


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[PATCH 1/2] RISC-V: make ISA string workaround case-insensitive

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
ISA string parsing").

Although the QEMU workaround in the ISA string parser works well with
lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
case-sensitive handling in the case-insensitive parser can be confusing.

This commit makes the QEMU workaround case-insensitive and gives more
robustness (against manually crafted Device Tree blobs) and less confusion
to kernel developers.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a8f66c015229..63277cdc1ea5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -168,19 +168,19 @@ void __init riscv_fill_hwcap(void)
 
 			switch (*ext) {
 			case 's':
+			case 'S':
 				/*
 				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
 				 * No need to set the bit in riscv_isa as 's' & 'u' are
 				 * not valid ISA extensions. It works until multi-letter
 				 * extension starting with "Su" appears.
 				 */
-				if (ext[-1] != '_' && ext[1] == 'u') {
+				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
 					++isa;
 					ext_err = true;
 					break;
 				}
 				fallthrough;
-			case 'S':
 			case 'x':
 			case 'X':
 			case 'z':
-- 
2.40.0


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Re: [PATCH 1/2] RISC-V: make ISA string workaround case-insensitive

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2117 bytes --]

On Sat, Jul 22, 2023 at 06:22:37AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
> ISA string parsing").
> 
> Although the QEMU workaround in the ISA string parser works well with
> lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
> case-sensitive handling in the case-insensitive parser can be confusing.

> This commit makes the QEMU workaround case-insensitive and gives more
> robustness (against manually crafted Device Tree blobs) and less confusion
> to kernel developers.

If people are manually crafting their DT, they should check it for
compliance with dt-validate (or dtbs_check). The case insensitivity only
makes sense for ACPI, but by the time ACPI was supported, you'd already
removed the "su" stuff from QEMU.

Thanks,
Conor.

> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index a8f66c015229..63277cdc1ea5 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -168,19 +168,19 @@ void __init riscv_fill_hwcap(void)
>  
>  			switch (*ext) {
>  			case 's':
> +			case 'S':
>  				/*
>  				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
>  				 * No need to set the bit in riscv_isa as 's' & 'u' are
>  				 * not valid ISA extensions. It works until multi-letter
>  				 * extension starting with "Su" appears.
>  				 */
> -				if (ext[-1] != '_' && ext[1] == 'u') {
> +				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
>  					++isa;
>  					ext_err = true;
>  					break;
>  				}
>  				fallthrough;
> -			case 'S':
>  			case 'x':
>  			case 'X':
>  			case 'z':
> -- 
> 2.40.0
> 
> 
> _______________________________________________
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> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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[PATCH 2/2] RISC-V: fix the comment for ISA string workaround

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Extensions prefixed with "Su" won't corrupt the workaround in many
cases.  The only exception is when the first multi-letter extension in the
ISA string begins with "Su" and is not prefixed with an underscore.

For instance, following ISA string can confuse this QEMU workaround.

*   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")

However, this case is very unlikely because extensions prefixed by either
"Z", "Sm" or "Ss" will most likely precede first.

For instance, the "Suclic" extension (draft as of now) will be placed after
related "Smclic" and "Ssclic" extensions.  It's also highly likely that
other unprivileged extensions like "Zba" will precede.

It's also possible to suppress the issue in the QEMU workaround with an
underscore.  Following ISA string won't confuse the QEMU workaround.

*   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")

This fix is to tell kernel developers the nature of this workaround
precisely.  There are some "Su*" extensions to be ratified but don't worry
about this workaround too much.

This commit comes with another minor editorial fix.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 63277cdc1ea5..91f1ef3e762c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -170,10 +170,11 @@ void __init riscv_fill_hwcap(void)
 			case 's':
 			case 'S':
 				/*
-				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
-				 * No need to set the bit in riscv_isa as 's' & 'u' are
-				 * not valid ISA extensions. It works until multi-letter
-				 * extension starting with "Su" appears.
+				 * Workaround for invalid single-letters 's' & 'u' (QEMU).
+				 * No need to set the bits in riscv_isa as 's' and 'u' are
+				 * not valid ISA extensions. It works unless the first multi-letter
+				 * extension in the ISA string begins with "Su" and not prefixed
+				 * with an underscore.
 				 */
 				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
 					++isa;
-- 
2.40.0


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Re: [PATCH 2/2] RISC-V: fix the comment for ISA string workaround

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2746 bytes --]

On Sat, Jul 22, 2023 at 06:22:38AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> Extensions prefixed with "Su" won't corrupt the workaround in many
> cases.  The only exception is when the first multi-letter extension in the
> ISA string begins with "Su" and is not prefixed with an underscore.
> 
> For instance, following ISA string can confuse this QEMU workaround.
> 
> *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
> 
> However, this case is very unlikely because extensions prefixed by either
> "Z", "Sm" or "Ss" will most likely precede first.
> 
> For instance, the "Suclic" extension (draft as of now) will be placed after
> related "Smclic" and "Ssclic" extensions.  It's also highly likely that
> other unprivileged extensions like "Zba" will precede.
> 
> It's also possible to suppress the issue in the QEMU workaround with an
> underscore.  Following ISA string won't confuse the QEMU workaround.
> 
> *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
> 
> This fix is to tell kernel developers the nature of this workaround
> precisely.  There are some "Su*" extensions to be ratified but don't worry
> about this workaround too much.
> 

> This commit comes with another minor editorial fix.

Which is what?

The new wording is fine by me though..
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 63277cdc1ea5..91f1ef3e762c 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -170,10 +170,11 @@ void __init riscv_fill_hwcap(void)
>  			case 's':
>  			case 'S':
>  				/*
> -				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
> -				 * No need to set the bit in riscv_isa as 's' & 'u' are
> -				 * not valid ISA extensions. It works until multi-letter
> -				 * extension starting with "Su" appears.
> +				 * Workaround for invalid single-letters 's' & 'u' (QEMU).
> +				 * No need to set the bits in riscv_isa as 's' and 'u' are
> +				 * not valid ISA extensions. It works unless the first multi-letter
> +				 * extension in the ISA string begins with "Su" and not prefixed
> +				 * with an underscore.
>  				 */
>  				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
>  					++isa;
> -- 
> 2.40.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [PATCH 2/2] RISC-V: fix the comment for ISA string workaround

[Tsukasa OI]

On 2023/07/22 19:52, Conor Dooley wrote:
> On Sat, Jul 22, 2023 at 06:22:38AM +0000, Tsukasa OI wrote:
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> Extensions prefixed with "Su" won't corrupt the workaround in many
>> cases.  The only exception is when the first multi-letter extension in the
>> ISA string begins with "Su" and is not prefixed with an underscore.
>>
>> For instance, following ISA string can confuse this QEMU workaround.
>>
>> *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
>>
>> However, this case is very unlikely because extensions prefixed by either
>> "Z", "Sm" or "Ss" will most likely precede first.
>>
>> For instance, the "Suclic" extension (draft as of now) will be placed after
>> related "Smclic" and "Ssclic" extensions.  It's also highly likely that
>> other unprivileged extensions like "Zba" will precede.
>>
>> It's also possible to suppress the issue in the QEMU workaround with an
>> underscore.  Following ISA string won't confuse the QEMU workaround.
>>
>> *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
>>
>> This fix is to tell kernel developers the nature of this workaround
>> precisely.  There are some "Su*" extensions to be ratified but don't worry
>> about this workaround too much.
>>
> 
>> This commit comes with another minor editorial fix.
> 
> Which is what?
> 
> The new wording is fine by me though..
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

1. Use of plurals ("letters" and "bits")
2. Second "'s' & 'u'" to "'s' and 'u'"
3. Spacing after the first "'s' & 'u'" (before "(QEMU).")

It feels they are too minor to separate to another commit.
At least I should replace the commit message to "other minor editorial
fixes" and... should I clarify editorial fixes?

Thanks,
Tsukasa

> 
> Thanks,
> Conor.
> 
>> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
>> ---
>>  arch/riscv/kernel/cpufeature.c | 9 +++++----
>>  1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index 63277cdc1ea5..91f1ef3e762c 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -170,10 +170,11 @@ void __init riscv_fill_hwcap(void)
>>  			case 's':
>>  			case 'S':
>>  				/*
>> -				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
>> -				 * No need to set the bit in riscv_isa as 's' & 'u' are
>> -				 * not valid ISA extensions. It works until multi-letter
>> -				 * extension starting with "Su" appears.
>> +				 * Workaround for invalid single-letters 's' & 'u' (QEMU).
>> +				 * No need to set the bits in riscv_isa as 's' and 'u' are
>> +				 * not valid ISA extensions. It works unless the first multi-letter
>> +				 * extension in the ISA string begins with "Su" and not prefixed
>> +				 * with an underscore.
>>  				 */
>>  				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
>>  					++isa;
>> -- 
>> 2.40.0
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [PATCH 2/2] RISC-V: fix the comment for ISA string workaround

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2401 bytes --]

On Sat, Jul 22, 2023 at 08:22:25PM +0900, Tsukasa OI wrote:
> 
> 
> On 2023/07/22 19:52, Conor Dooley wrote:
> > On Sat, Jul 22, 2023 at 06:22:38AM +0000, Tsukasa OI wrote:
> >> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> >>
> >> Extensions prefixed with "Su" won't corrupt the workaround in many
> >> cases.  The only exception is when the first multi-letter extension in the
> >> ISA string begins with "Su" and is not prefixed with an underscore.
> >>
> >> For instance, following ISA string can confuse this QEMU workaround.
> >>
> >> *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
> >>
> >> However, this case is very unlikely because extensions prefixed by either
> >> "Z", "Sm" or "Ss" will most likely precede first.
> >>
> >> For instance, the "Suclic" extension (draft as of now) will be placed after
> >> related "Smclic" and "Ssclic" extensions.  It's also highly likely that
> >> other unprivileged extensions like "Zba" will precede.
> >>
> >> It's also possible to suppress the issue in the QEMU workaround with an
> >> underscore.  Following ISA string won't confuse the QEMU workaround.
> >>
> >> *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
> >>
> >> This fix is to tell kernel developers the nature of this workaround
> >> precisely.  There are some "Su*" extensions to be ratified but don't worry
> >> about this workaround too much.
> >>
> > 
> >> This commit comes with another minor editorial fix.
> > 
> > Which is what?
> > 
> > The new wording is fine by me though..
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> 1. Use of plurals ("letters" and "bits")
> 2. Second "'s' & 'u'" to "'s' and 'u'"
> 3. Spacing after the first "'s' & 'u'" (before "(QEMU).")
> 
> It feels they are too minor to separate to another commit.
> At least I should replace the commit message to "other minor editorial
> fixes" and... should I clarify editorial fixes?

I dunno, I just wasn't sure what you meant.

> >> +				 * Workaround for invalid single-letters 's' & 'u' (QEMU).
> >> +				 * No need to set the bits in riscv_isa as 's' and 'u' are
> >> +				 * not valid ISA extensions. It works unless the first multi-letter
> >> +				 * extension in the ISA string begins with "Su" and not prefixed

Re-reading I noticed this should be "is not prefixed".

> >> +				 * with an underscore.


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[PATCH v2 0/1] RISC-V: clarification of the QEMU workaround in the ISA parser

[Tsukasa OI]

Hello,

This is the PATCH v2 to clarify the intent and a non-working example of the
QEMU workaround in the RISC-V ISA parser.  Along with comment fixes, I hope
the commit message itself should be helpful to understand the workaround
in the ISA string parser.

v1:
(the initial submission; see the each PATCH for details)

v2:
*   PATCH 1/2 is withdrawn for now
    (now only comment fix; previously PATCH 2/2)
*   Other grammar fixes
*   Clarification of the commit message




Tsukasa OI (1):
  RISC-V: clarify the QEMU workaround in ISA parser

 arch/riscv/kernel/cpufeature.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

-- 
2.41.0


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[PATCH v2 1/1] RISC-V: clarify the QEMU workaround in ISA parser

[Tsukasa OI]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

Extensions prefixed with "Su" won't corrupt the workaround in many
cases.  The only exception is when the first multi-letter extension in the
ISA string begins with "Su" and is not prefixed with an underscore.

For instance, following ISA string can confuse this QEMU workaround.

*   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")

However, this case is very unlikely because extensions prefixed by either
"Z", "Sm" or "Ss" will most likely precede first.

For instance, the "Suclic" extension (draft as of now) will be placed after
related "Smclic" and "Ssclic" extensions.  It's also highly likely that
other unprivileged extensions like "Zba" will precede.

It's also possible to suppress the issue in the QEMU workaround with an
underscore.  Following ISA string won't confuse the QEMU workaround.

*   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")

This fix is to tell kernel developers the nature of this workaround
precisely.  There are some "Su*" extensions to be ratified but don't worry
about this workaround too much.

This commit comes with other minor editorial fixes (for minor wording and
spacing issues, without changing the meaning).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a8f66c015229..5b2ac109980c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -169,10 +169,11 @@ void __init riscv_fill_hwcap(void)
 			switch (*ext) {
 			case 's':
 				/*
-				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
-				 * No need to set the bit in riscv_isa as 's' & 'u' are
-				 * not valid ISA extensions. It works until multi-letter
-				 * extension starting with "Su" appears.
+				 * Workaround for invalid single-letters 's' & 'u' (QEMU).
+				 * No need to set the bits in riscv_isa as 's' and 'u' are
+				 * not valid ISA extensions. It works unless the first multi-letter
+				 * extension in the ISA string begins with "Su" and is not prefixed
+				 * with an underscore.
 				 */
 				if (ext[-1] != '_' && ext[1] == 'u') {
 					++isa;
-- 
2.41.0


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Re: [PATCH v2 1/1] RISC-V: clarify the QEMU workaround in ISA parser

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1564 bytes --]

On Wed, Jul 26, 2023 at 05:44:16AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> Extensions prefixed with "Su" won't corrupt the workaround in many
> cases.  The only exception is when the first multi-letter extension in the
> ISA string begins with "Su" and is not prefixed with an underscore.
> 
> For instance, following ISA string can confuse this QEMU workaround.
> 
> *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
> 
> However, this case is very unlikely because extensions prefixed by either
> "Z", "Sm" or "Ss" will most likely precede first.
> 
> For instance, the "Suclic" extension (draft as of now) will be placed after
> related "Smclic" and "Ssclic" extensions.  It's also highly likely that
> other unprivileged extensions like "Zba" will precede.
> 
> It's also possible to suppress the issue in the QEMU workaround with an
> underscore.  Following ISA string won't confuse the QEMU workaround.
> 
> *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
> 
> This fix is to tell kernel developers the nature of this workaround
> precisely.  There are some "Su*" extensions to be ratified but don't worry
> about this workaround too much.
> 
> This commit comes with other minor editorial fixes (for minor wording and
> spacing issues, without changing the meaning).
> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Pretty sure I gave you a Reviewed-by last time? Nevertheless,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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