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Fri, 24 May 2024 12:34:59 -0700 (PDT) Received: from tjeznach.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fd4d878esm1441684b3a.190.2024.05.24.12.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 12:34:59 -0700 (PDT) From: Tomasz Jeznach To: Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley Subject: [PATCH v6 0/7] Linux RISC-V IOMMU Support Date: Fri, 24 May 2024 12:34:40 -0700 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_123502_213800_95F969B4 X-CRM114-Status: GOOD ( 15.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , devicetree@vger.kernel.org, Conor Dooley , Albert Ou , Tomasz Jeznach , linux@rivosinc.com, linux-kernel@vger.kernel.org, Rob Herring , Sebastien Boeuf , iommu@lists.linux.dev, Palmer Dabbelt , Nick Kossifidis , Krzysztof Kozlowski , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch series introduces support for RISC-V IOMMU architected hardware into the Linux kernel. The RISC-V IOMMU specification, which this series is based on, is ratified and available at GitHub/riscv-non-isa [1]. At a high level, the RISC-V IOMMU specification defines: 1) Data structures: - Device-context: Associates devices with address spaces and holds per-device parameters for address translations. - Process-contexts: Associates different virtual address spaces based on device-provided process identification numbers. - MSI page table configuration used to direct an MSI to a guest interrupt file in an IMSIC. 2) In-memory queue interface: - Command-queue for issuing commands to the IOMMU. - Fault/event queue for reporting faults and events. - Page-request queue for reporting "Page Request" messages received from PCIe devices. - Message-signaled and wire-signaled interrupt mechanisms. 3) Memory-mapped programming interface: - Mandatory and optional register layout and description. - Software guidelines for device initialization and capabilities discovery. This series introduces RISC-V IOMMU hardware initialization and complete single-stage translation with paging domain support. The patches are organized as follows: Patch 1: Introduces minimal required device tree bindings for the driver. Patch 2: Defines RISC-V IOMMU data structures, hardware programming interface registers layout, and minimal initialization code for enabling global pass-through for all connected masters. Patch 3: Implements the device driver for PCIe implementation of RISC-V IOMMU architected hardware. Patch 4: Introduces IOMMU interfaces to the kernel subsystem. Patch 5: Implements device directory management with discovery sequences for I/O mapped or in-memory device directory table location, hardware capabilities discovery, and device to domain attach implementation. Patch 6: Implements command and fault queue, and introduces directory cache invalidation sequences. Patch 7: Implements paging domain, using highest page-table mode advertised by the hardware. This series enables only 4K mappings; complete support for large page mappings will be introduced in follow-up patch series. Follow-up patch series, providing large page support and updated walk cache management based on the revised specification, and complete ATS/PRI/SVA support, will be posted to GitHub [2]. Changes from v5: - rebase on master - fix dc.tc.v check in riscv_iommu_iodir_update() - fix to use list_for_each_entry (without _rcu) under lock - editorial changes: comment spelling Best regards, Tomasz Jeznach [1] link: https://github.com/riscv-non-isa/riscv-iommu [2] link: https://github.com/tjeznach/linux v5 link: https://lore.kernel.org/linux-iommu/cover.1715708679.git.tjeznach@rivosinc.com/ v4 link: https://lore.kernel.org/linux-iommu/cover.1714752293.git.tjeznach@rivosinc.com/ v3 link: https://lore.kernel.org/linux-iommu/cover.1714494653.git.tjeznach@rivosinc.com/ v2 link: https://lore.kernel.org/linux-iommu/cover.1713456597.git.tjeznach@rivosinc.com/ v1 link: https://lore.kernel.org/linux-iommu/cover.1689792825.git.tjeznach@rivosinc.com/ Tomasz Jeznach (7): dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU iommu/riscv: Add RISC-V IOMMU platform device driver iommu/riscv: Add RISC-V IOMMU PCIe device driver iommu/riscv: Enable IOMMU registration and device probe. iommu/riscv: Device directory management. iommu/riscv: Command and fault queue support iommu/riscv: Paging domain support .../bindings/iommu/riscv,iommu.yaml | 147 ++ MAINTAINERS | 8 + drivers/iommu/Kconfig | 1 + drivers/iommu/Makefile | 2 +- drivers/iommu/riscv/Kconfig | 20 + drivers/iommu/riscv/Makefile | 3 + drivers/iommu/riscv/iommu-bits.h | 782 ++++++++ drivers/iommu/riscv/iommu-pci.c | 119 ++ drivers/iommu/riscv/iommu-platform.c | 92 + drivers/iommu/riscv/iommu.c | 1674 +++++++++++++++++ drivers/iommu/riscv/iommu.h | 88 + 11 files changed, 2935 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml create mode 100644 drivers/iommu/riscv/Kconfig create mode 100644 drivers/iommu/riscv/Makefile create mode 100644 drivers/iommu/riscv/iommu-bits.h create mode 100644 drivers/iommu/riscv/iommu-pci.c create mode 100644 drivers/iommu/riscv/iommu-platform.c create mode 100644 drivers/iommu/riscv/iommu.c create mode 100644 drivers/iommu/riscv/iommu.h base-commit: f1f9984fdc5e37303d7180ff7a85dfecb8e57e85 -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv