* [PATCH 0/4] RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests
@ 2024-11-28 3:20 zhouquan
2024-11-28 3:21 ` [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM zhouquan
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: zhouquan @ 2024-11-28 3:20 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer, aou
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Advertise Svvptc/Zabha/Ziccrse extensions to KVM guest
when underlying host supports it.
Quan Zhou (4):
RISC-V: KVM: Allow Svvptc extension for Guest/VM
RISC-V: KVM: Allow Zabha extension for Guest/VM
RISC-V: KVM: Allow Ziccrse extension for Guest/VM
KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list
test
arch/riscv/include/uapi/asm/kvm.h | 3 +++
arch/riscv/kvm/vcpu_onereg.c | 6 ++++++
tools/testing/selftests/kvm/riscv/get-reg-list.c | 12 ++++++++++++
3 files changed, 21 insertions(+)
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM
2024-11-28 3:20 [PATCH 0/4] RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests zhouquan
@ 2024-11-28 3:21 ` zhouquan
2024-11-28 8:50 ` Andrew Jones
2024-11-28 3:21 ` [PATCH 2/4] RISC-V: KVM: Allow Zabha " zhouquan
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: zhouquan @ 2024-11-28 3:21 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer, aou
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Svvptc extension for Guest/VM.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 4f24201376b1..9db33f52f56e 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -177,6 +177,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_ZAWRS,
KVM_RISCV_ISA_EXT_SMNPM,
KVM_RISCV_ISA_EXT_SSNPM,
+ KVM_RISCV_ISA_EXT_SVVPTC,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 5b68490ad9b7..67965feb5b74 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -41,6 +41,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(SSNPM),
KVM_ISA_EXT_ARR(SSTC),
KVM_ISA_EXT_ARR(SVINVAL),
+ KVM_ISA_EXT_ARR(SVVPTC),
KVM_ISA_EXT_ARR(SVNAPOT),
KVM_ISA_EXT_ARR(SVPBMT),
KVM_ISA_EXT_ARR(ZACAS),
@@ -135,6 +136,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_SSNPM:
case KVM_RISCV_ISA_EXT_SSTC:
case KVM_RISCV_ISA_EXT_SVINVAL:
+ case KVM_RISCV_ISA_EXT_SVVPTC:
case KVM_RISCV_ISA_EXT_SVNAPOT:
case KVM_RISCV_ISA_EXT_ZACAS:
case KVM_RISCV_ISA_EXT_ZAWRS:
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/4] RISC-V: KVM: Allow Zabha extension for Guest/VM
2024-11-28 3:20 [PATCH 0/4] RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests zhouquan
2024-11-28 3:21 ` [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM zhouquan
@ 2024-11-28 3:21 ` zhouquan
2024-11-28 8:52 ` Andrew Jones
2024-11-28 3:22 ` [PATCH 3/4] RISC-V: KVM: Allow Ziccrse " zhouquan
2024-11-28 3:22 ` [PATCH 4/4] KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test zhouquan
3 siblings, 1 reply; 9+ messages in thread
From: zhouquan @ 2024-11-28 3:21 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer, aou
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Zabha extension for Guest/VM.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 9db33f52f56e..340618131249 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -178,6 +178,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_SMNPM,
KVM_RISCV_ISA_EXT_SSNPM,
KVM_RISCV_ISA_EXT_SVVPTC,
+ KVM_RISCV_ISA_EXT_ZABHA,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 67965feb5b74..9a30a98f30bc 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -44,6 +44,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(SVVPTC),
KVM_ISA_EXT_ARR(SVNAPOT),
KVM_ISA_EXT_ARR(SVPBMT),
+ KVM_ISA_EXT_ARR(ZABHA),
KVM_ISA_EXT_ARR(ZACAS),
KVM_ISA_EXT_ARR(ZAWRS),
KVM_ISA_EXT_ARR(ZBA),
@@ -138,6 +139,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_SVINVAL:
case KVM_RISCV_ISA_EXT_SVVPTC:
case KVM_RISCV_ISA_EXT_SVNAPOT:
+ case KVM_RISCV_ISA_EXT_ZABHA:
case KVM_RISCV_ISA_EXT_ZACAS:
case KVM_RISCV_ISA_EXT_ZAWRS:
case KVM_RISCV_ISA_EXT_ZBA:
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/4] RISC-V: KVM: Allow Ziccrse extension for Guest/VM
2024-11-28 3:20 [PATCH 0/4] RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests zhouquan
2024-11-28 3:21 ` [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM zhouquan
2024-11-28 3:21 ` [PATCH 2/4] RISC-V: KVM: Allow Zabha " zhouquan
@ 2024-11-28 3:22 ` zhouquan
2024-11-28 8:54 ` Andrew Jones
2024-11-28 3:22 ` [PATCH 4/4] KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test zhouquan
3 siblings, 1 reply; 9+ messages in thread
From: zhouquan @ 2024-11-28 3:22 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer, aou
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
Extend the KVM ISA extension ONE_REG interface to allow KVM user space
to detect and enable Ziccrse extension for Guest/VM.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 340618131249..f7afb4267148 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -179,6 +179,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_SSNPM,
KVM_RISCV_ISA_EXT_SVVPTC,
KVM_RISCV_ISA_EXT_ZABHA,
+ KVM_RISCV_ISA_EXT_ZICCRSE,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index 9a30a98f30bc..ed8e17da1536 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -64,6 +64,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
KVM_ISA_EXT_ARR(ZFHMIN),
KVM_ISA_EXT_ARR(ZICBOM),
KVM_ISA_EXT_ARR(ZICBOZ),
+ KVM_ISA_EXT_ARR(ZICCRSE),
KVM_ISA_EXT_ARR(ZICNTR),
KVM_ISA_EXT_ARR(ZICOND),
KVM_ISA_EXT_ARR(ZICSR),
@@ -157,6 +158,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
case KVM_RISCV_ISA_EXT_ZFA:
case KVM_RISCV_ISA_EXT_ZFH:
case KVM_RISCV_ISA_EXT_ZFHMIN:
+ case KVM_RISCV_ISA_EXT_ZICCRSE:
case KVM_RISCV_ISA_EXT_ZICNTR:
case KVM_RISCV_ISA_EXT_ZICOND:
case KVM_RISCV_ISA_EXT_ZICSR:
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/4] KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test
2024-11-28 3:20 [PATCH 0/4] RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests zhouquan
` (2 preceding siblings ...)
2024-11-28 3:22 ` [PATCH 3/4] RISC-V: KVM: Allow Ziccrse " zhouquan
@ 2024-11-28 3:22 ` zhouquan
2024-11-28 9:00 ` Andrew Jones
3 siblings, 1 reply; 9+ messages in thread
From: zhouquan @ 2024-11-28 3:22 UTC (permalink / raw)
To: anup, ajones, atishp, paul.walmsley, palmer, aou
Cc: linux-kernel, linux-riscv, kvm, kvm-riscv, Quan Zhou
From: Quan Zhou <zhouquan@iscas.ac.cn>
The KVM RISC-V allows Svvptc/Zabha/Ziccrse extensions for Guest/VM
so add them to get-reg-list test.
Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 54ab484d0000..a697db1ff411 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -48,8 +48,10 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
@@ -69,6 +71,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
+ case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
@@ -423,8 +426,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(SSNPM),
KVM_ISA_EXT_ARR(SSTC),
KVM_ISA_EXT_ARR(SVINVAL),
+ KVM_ISA_EXT_ARR(SVVPTC),
KVM_ISA_EXT_ARR(SVNAPOT),
KVM_ISA_EXT_ARR(SVPBMT),
+ KVM_ISA_EXT_ARR(ZABHA),
KVM_ISA_EXT_ARR(ZACAS),
KVM_ISA_EXT_ARR(ZAWRS),
KVM_ISA_EXT_ARR(ZBA),
@@ -444,6 +449,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
KVM_ISA_EXT_ARR(ZFHMIN),
KVM_ISA_EXT_ARR(ZICBOM),
KVM_ISA_EXT_ARR(ZICBOZ),
+ KVM_ISA_EXT_ARR(ZICCRSE),
KVM_ISA_EXT_ARR(ZICNTR),
KVM_ISA_EXT_ARR(ZICOND),
KVM_ISA_EXT_ARR(ZICSR),
@@ -956,8 +962,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM);
KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
+KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);
KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
+KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
@@ -977,6 +985,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
+KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
@@ -1021,8 +1030,10 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_ssnpm,
&config_sstc,
&config_svinval,
+ &config_svvptc,
&config_svnapot,
&config_svpbmt,
+ &config_zabha,
&config_zacas,
&config_zawrs,
&config_zba,
@@ -1042,6 +1053,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
&config_zfhmin,
&config_zicbom,
&config_zicboz,
+ &config_ziccrse,
&config_zicntr,
&config_zicond,
&config_zicsr,
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM
2024-11-28 3:21 ` [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM zhouquan
@ 2024-11-28 8:50 ` Andrew Jones
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jones @ 2024-11-28 8:50 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, aou, linux-kernel,
linux-riscv, kvm, kvm-riscv
On Thu, Nov 28, 2024 at 11:21:15AM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Svvptc extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 4f24201376b1..9db33f52f56e 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -177,6 +177,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZAWRS,
> KVM_RISCV_ISA_EXT_SMNPM,
> KVM_RISCV_ISA_EXT_SSNPM,
> + KVM_RISCV_ISA_EXT_SVVPTC,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 5b68490ad9b7..67965feb5b74 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -41,6 +41,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(SSNPM),
> KVM_ISA_EXT_ARR(SSTC),
> KVM_ISA_EXT_ARR(SVINVAL),
> + KVM_ISA_EXT_ARR(SVVPTC),
Alphabetic order, please.
> KVM_ISA_EXT_ARR(SVNAPOT),
> KVM_ISA_EXT_ARR(SVPBMT),
> KVM_ISA_EXT_ARR(ZACAS),
> @@ -135,6 +136,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_SSNPM:
> case KVM_RISCV_ISA_EXT_SSTC:
> case KVM_RISCV_ISA_EXT_SVINVAL:
> + case KVM_RISCV_ISA_EXT_SVVPTC:
Same comment as above.
> case KVM_RISCV_ISA_EXT_SVNAPOT:
> case KVM_RISCV_ISA_EXT_ZACAS:
> case KVM_RISCV_ISA_EXT_ZAWRS:
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] RISC-V: KVM: Allow Zabha extension for Guest/VM
2024-11-28 3:21 ` [PATCH 2/4] RISC-V: KVM: Allow Zabha " zhouquan
@ 2024-11-28 8:52 ` Andrew Jones
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jones @ 2024-11-28 8:52 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, aou, linux-kernel,
linux-riscv, kvm, kvm-riscv
On Thu, Nov 28, 2024 at 11:21:26AM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zabha extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 9db33f52f56e..340618131249 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -178,6 +178,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_SMNPM,
> KVM_RISCV_ISA_EXT_SSNPM,
> KVM_RISCV_ISA_EXT_SVVPTC,
> + KVM_RISCV_ISA_EXT_ZABHA,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 67965feb5b74..9a30a98f30bc 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -44,6 +44,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(SVVPTC),
> KVM_ISA_EXT_ARR(SVNAPOT),
> KVM_ISA_EXT_ARR(SVPBMT),
> + KVM_ISA_EXT_ARR(ZABHA),
> KVM_ISA_EXT_ARR(ZACAS),
> KVM_ISA_EXT_ARR(ZAWRS),
> KVM_ISA_EXT_ARR(ZBA),
> @@ -138,6 +139,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_SVINVAL:
> case KVM_RISCV_ISA_EXT_SVVPTC:
> case KVM_RISCV_ISA_EXT_SVNAPOT:
> + case KVM_RISCV_ISA_EXT_ZABHA:
> case KVM_RISCV_ISA_EXT_ZACAS:
> case KVM_RISCV_ISA_EXT_ZAWRS:
> case KVM_RISCV_ISA_EXT_ZBA:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] RISC-V: KVM: Allow Ziccrse extension for Guest/VM
2024-11-28 3:22 ` [PATCH 3/4] RISC-V: KVM: Allow Ziccrse " zhouquan
@ 2024-11-28 8:54 ` Andrew Jones
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jones @ 2024-11-28 8:54 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, aou, linux-kernel,
linux-riscv, kvm, kvm-riscv
On Thu, Nov 28, 2024 at 11:22:07AM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Ziccrse extension for Guest/VM.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 340618131249..f7afb4267148 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -179,6 +179,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_SSNPM,
> KVM_RISCV_ISA_EXT_SVVPTC,
> KVM_RISCV_ISA_EXT_ZABHA,
> + KVM_RISCV_ISA_EXT_ZICCRSE,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 9a30a98f30bc..ed8e17da1536 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -64,6 +64,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> KVM_ISA_EXT_ARR(ZICBOZ),
> + KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> KVM_ISA_EXT_ARR(ZICOND),
> KVM_ISA_EXT_ARR(ZICSR),
> @@ -157,6 +158,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZFA:
> case KVM_RISCV_ISA_EXT_ZFH:
> case KVM_RISCV_ISA_EXT_ZFHMIN:
> + case KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_RISCV_ISA_EXT_ZICNTR:
> case KVM_RISCV_ISA_EXT_ZICOND:
> case KVM_RISCV_ISA_EXT_ZICSR:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 4/4] KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test
2024-11-28 3:22 ` [PATCH 4/4] KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test zhouquan
@ 2024-11-28 9:00 ` Andrew Jones
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jones @ 2024-11-28 9:00 UTC (permalink / raw)
To: zhouquan
Cc: anup, atishp, paul.walmsley, palmer, aou, linux-kernel,
linux-riscv, kvm, kvm-riscv
On Thu, Nov 28, 2024 at 11:22:14AM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
>
> The KVM RISC-V allows Svvptc/Zabha/Ziccrse extensions for Guest/VM
> so add them to get-reg-list test.
>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 54ab484d0000..a697db1ff411 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -48,8 +48,10 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC:
Alphabetic order, please.
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
> @@ -69,6 +71,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
> @@ -423,8 +426,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(SSNPM),
> KVM_ISA_EXT_ARR(SSTC),
> KVM_ISA_EXT_ARR(SVINVAL),
> + KVM_ISA_EXT_ARR(SVVPTC),
Same comment as above.
> KVM_ISA_EXT_ARR(SVNAPOT),
> KVM_ISA_EXT_ARR(SVPBMT),
> + KVM_ISA_EXT_ARR(ZABHA),
> KVM_ISA_EXT_ARR(ZACAS),
> KVM_ISA_EXT_ARR(ZAWRS),
> KVM_ISA_EXT_ARR(ZBA),
> @@ -444,6 +449,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZFHMIN),
> KVM_ISA_EXT_ARR(ZICBOM),
> KVM_ISA_EXT_ARR(ZICBOZ),
> + KVM_ISA_EXT_ARR(ZICCRSE),
> KVM_ISA_EXT_ARR(ZICNTR),
> KVM_ISA_EXT_ARR(ZICOND),
> KVM_ISA_EXT_ARR(ZICSR),
> @@ -956,8 +962,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
> KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM);
> KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
> KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
> +KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);
Same comment as above.
> KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
> KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
> KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
> KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
> @@ -977,6 +985,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
> KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
> KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
> +KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
> KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
> @@ -1021,8 +1030,10 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_ssnpm,
> &config_sstc,
> &config_svinval,
> + &config_svvptc,
Same comment as above.
> &config_svnapot,
> &config_svpbmt,
> + &config_zabha,
> &config_zacas,
> &config_zawrs,
> &config_zba,
> @@ -1042,6 +1053,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zfhmin,
> &config_zicbom,
> &config_zicboz,
> + &config_ziccrse,
> &config_zicntr,
> &config_zicond,
> &config_zicsr,
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-11-28 9:00 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-28 3:20 [PATCH 0/4] RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests zhouquan
2024-11-28 3:21 ` [PATCH 1/4] RISC-V: KVM: Allow Svvptc extension for Guest/VM zhouquan
2024-11-28 8:50 ` Andrew Jones
2024-11-28 3:21 ` [PATCH 2/4] RISC-V: KVM: Allow Zabha " zhouquan
2024-11-28 8:52 ` Andrew Jones
2024-11-28 3:22 ` [PATCH 3/4] RISC-V: KVM: Allow Ziccrse " zhouquan
2024-11-28 8:54 ` Andrew Jones
2024-11-28 3:22 ` [PATCH 4/4] KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test zhouquan
2024-11-28 9:00 ` Andrew Jones
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