* [PATCH 0/3] riscv: soc: re-organized allwinner
@ 2025-11-08 8:20 gaohan
2025-11-08 8:20 ` [PATCH 1/3] riscv: soc: re-organized allwinner menu gaohan
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: gaohan @ 2025-11-08 8:20 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Han Gao, Yixun Lan, Drew Fustini,
Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley
Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel,
linux-sunxi, Han Gao
From: Han Gao <gaohan@iscas.ac.cn>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V,
using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Han Gao (3):
riscv: soc: re-organized allwinner menu
riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE
riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES
arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
arch/riscv/boot/dts/allwinner/Makefile | 20 ++++++++++----------
arch/riscv/configs/defconfig | 2 ++
3 files changed, 29 insertions(+), 15 deletions(-)
--
2.47.3
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 8:20 [PATCH 0/3] riscv: soc: re-organized allwinner gaohan @ 2025-11-08 8:20 ` gaohan 2025-11-08 11:29 ` Krzysztof Kozlowski 2025-11-08 8:20 ` [PATCH 2/3] riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE gaohan ` (2 subsequent siblings) 3 siblings, 1 reply; 12+ messages in thread From: gaohan @ 2025-11-08 8:20 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Han Gao, Yixun Lan, Drew Fustini, Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao From: Han Gao <gaohan@iscas.ac.cn> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs. d1(s): Xuantie C906 v821: Andes A27 + XuanTie E907 v861/v881: XuanTie C907 Signed-off-by: Han Gao <gaohan@iscas.ac.cn> --- arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 848e7149e443..7cba5d6ec4c3 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -54,14 +54,26 @@ config SOC_STARFIVE help This enables support for StarFive SoC platform hardware. -config ARCH_SUNXI - bool "Allwinner sun20i SoCs" +menuconfig ARCH_SUNXI + bool "Allwinner RISC-V SoCs" + +if ARCH_SUNXI + +config ARCH_SUNXI_XUANTIE + bool "Allwinner Xuantie IP SoCs" depends on MMU && !XIP_KERNEL - select ERRATA_THEAD select SUN4I_TIMER + select ERRATA_THEAD help - This enables support for Allwinner sun20i platform hardware, - including boards based on the D1 and D1s SoCs. + This enables support for Allwinner Xuantie IP SoCs. + +config ARCH_SUNXI_ANDES + bool "Allwinner Andes IP SoCs" + select ERRATA_ANDES + help + This enables support for Allwinner Andes IP SoCs. + +endif config ARCH_THEAD bool "T-HEAD RISC-V SoCs" -- 2.47.3 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 8:20 ` [PATCH 1/3] riscv: soc: re-organized allwinner menu gaohan @ 2025-11-08 11:29 ` Krzysztof Kozlowski 2025-11-08 13:59 ` revy 0 siblings, 1 reply; 12+ messages in thread From: Krzysztof Kozlowski @ 2025-11-08 11:29 UTC (permalink / raw) To: gaohan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: > From: Han Gao <gaohan@iscas.ac.cn> > > Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, > using different IPs. > > d1(s): Xuantie C906 > v821: Andes A27 + XuanTie E907 > v861/v881: XuanTie C907 > > Signed-off-by: Han Gao <gaohan@iscas.ac.cn> > --- > arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 848e7149e443..7cba5d6ec4c3 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -54,14 +54,26 @@ config SOC_STARFIVE > help > This enables support for StarFive SoC platform hardware. > > -config ARCH_SUNXI > - bool "Allwinner sun20i SoCs" > +menuconfig ARCH_SUNXI > + bool "Allwinner RISC-V SoCs" > + > +if ARCH_SUNXI > + > +config ARCH_SUNXI_XUANTIE You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 11:29 ` Krzysztof Kozlowski @ 2025-11-08 13:59 ` revy 2025-11-08 14:47 ` Krzysztof Kozlowski 0 siblings, 1 reply; 12+ messages in thread From: revy @ 2025-11-08 13:59 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, krzk+dt, conor+dt, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, geert+renesas, Guodong Xu, Haylen Chu, Joel Stanley, linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao > -----Original Messages----- > From: "Krzysztof Kozlowski" <krzk@kernel.org> > Sent Time: 2025-11-08 19:29:07 (Saturday) > To: gaohan@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alex@ghiti.fr>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>, "Jernej Skrabec" <jernej.skrabec@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Yixun Lan" <dlan@gentoo.org>, "Drew Fustini" <fustini@kernel.org>, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Guodong Xu" <guodong@riscstar.com>, "Haylen Chu" <heylenay@4d2.org>, "Joel Stanley" <joel@jms.id.au> > Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" <rabenda.cn@gmail.com> > Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu > > On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: >> From: Han Gao <gaohan@iscas.ac.cn> >> >> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, >> using different IPs. >> >> d1(s): Xuantie C906 >> v821: Andes A27 + XuanTie E907 >> v861/v881: XuanTie C907 >> >> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> >> --- >> arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >> index 848e7149e443..7cba5d6ec4c3 100644 >> --- a/arch/riscv/Kconfig.socs >> +++ b/arch/riscv/Kconfig.socs >> @@ -54,14 +54,26 @@ config SOC_STARFIVE >> help >> This enables support for StarFive SoC platform hardware. >> >> -config ARCH_SUNXI >> - bool "Allwinner sun20i SoCs" >> +menuconfig ARCH_SUNXI >> + bool "Allwinner RISC-V SoCs" >> + >> +if ARCH_SUNXI >> + >> +config ARCH_SUNXI_XUANTIE > > > You should not get multiple ARCHs. ARCH is only one. There is also not > much rationale in commit msg for that. The main goal is to avoid choosing multiple IP addresses for erreta. If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA. For example, v821 uses Andes ax27, but it used to select ERRATA_THEAD. > > Best regards, > Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 13:59 ` revy @ 2025-11-08 14:47 ` Krzysztof Kozlowski 2025-11-08 14:48 ` Krzysztof Kozlowski 0 siblings, 1 reply; 12+ messages in thread From: Krzysztof Kozlowski @ 2025-11-08 14:47 UTC (permalink / raw) To: revy Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, krzk+dt, conor+dt, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, geert+renesas, Guodong Xu, Haylen Chu, Joel Stanley, linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao On 08/11/2025 14:59, revy wrote: > > > >> -----Original Messages----- >> From: "Krzysztof Kozlowski" <krzk@kernel.org> >> Sent Time: 2025-11-08 19:29:07 (Saturday) >> To: gaohan@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alex@ghiti.fr>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>, "Jernej Skrabec" <jernej.skrabec@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Yixun Lan" <dlan@gentoo.org>, "Drew Fustini" <fustini@kernel.org>, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Guodong Xu" <guodong@riscstar.com>, "Haylen Chu" <heylenay@4d2.org>, "Joel Stanley" <joel@jms.id.au> >> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" <rabenda.cn@gmail.com> >> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu >> >> On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: >>> From: Han Gao <gaohan@iscas.ac.cn> >>> >>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, >>> using different IPs. >>> >>> d1(s): Xuantie C906 >>> v821: Andes A27 + XuanTie E907 >>> v861/v881: XuanTie C907 >>> >>> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> >>> --- >>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- >>> 1 file changed, 17 insertions(+), 5 deletions(-) >>> >>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >>> index 848e7149e443..7cba5d6ec4c3 100644 >>> --- a/arch/riscv/Kconfig.socs >>> +++ b/arch/riscv/Kconfig.socs >>> @@ -54,14 +54,26 @@ config SOC_STARFIVE >>> help >>> This enables support for StarFive SoC platform hardware. >>> >>> -config ARCH_SUNXI >>> - bool "Allwinner sun20i SoCs" >>> +menuconfig ARCH_SUNXI >>> + bool "Allwinner RISC-V SoCs" >>> + >>> +if ARCH_SUNXI >>> + >>> +config ARCH_SUNXI_XUANTIE >> >> >> You should not get multiple ARCHs. ARCH is only one. There is also not >> much rationale in commit msg for that. > > The main goal is to avoid choosing multiple IP addresses for erreta. > If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA. Not explained in commit msg but anyway not a good argument. It is some sort of micro optimization and you completely miss the point we target multiarch kernels. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 14:47 ` Krzysztof Kozlowski @ 2025-11-08 14:48 ` Krzysztof Kozlowski 2025-11-08 16:23 ` Conor Dooley 0 siblings, 1 reply; 12+ messages in thread From: Krzysztof Kozlowski @ 2025-11-08 14:48 UTC (permalink / raw) To: revy Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, krzk+dt, conor+dt, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, geert+renesas, Guodong Xu, Haylen Chu, Joel Stanley, linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao On 08/11/2025 15:47, Krzysztof Kozlowski wrote: > On 08/11/2025 14:59, revy wrote: >> >> >> >>> -----Original Messages----- >>> From: "Krzysztof Kozlowski" <krzk@kernel.org> >>> Sent Time: 2025-11-08 19:29:07 (Saturday) >>> To: gaohan@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alex@ghiti.fr>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>, "Jernej Skrabec" <jernej.skrabec@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Yixun Lan" <dlan@gentoo.org>, "Drew Fustini" <fustini@kernel.org>, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Guodong Xu" <guodong@riscstar.com>, "Haylen Chu" <heylenay@4d2.org>, "Joel Stanley" <joel@jms.id.au> >>> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" <rabenda.cn@gmail.com> >>> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu >>> >>> On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: >>>> From: Han Gao <gaohan@iscas.ac.cn> >>>> >>>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, >>>> using different IPs. >>>> >>>> d1(s): Xuantie C906 >>>> v821: Andes A27 + XuanTie E907 >>>> v861/v881: XuanTie C907 >>>> >>>> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> >>>> --- >>>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- >>>> 1 file changed, 17 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >>>> index 848e7149e443..7cba5d6ec4c3 100644 >>>> --- a/arch/riscv/Kconfig.socs >>>> +++ b/arch/riscv/Kconfig.socs >>>> @@ -54,14 +54,26 @@ config SOC_STARFIVE >>>> help >>>> This enables support for StarFive SoC platform hardware. >>>> >>>> -config ARCH_SUNXI >>>> - bool "Allwinner sun20i SoCs" >>>> +menuconfig ARCH_SUNXI >>>> + bool "Allwinner RISC-V SoCs" >>>> + >>>> +if ARCH_SUNXI >>>> + >>>> +config ARCH_SUNXI_XUANTIE >>> >>> >>> You should not get multiple ARCHs. ARCH is only one. There is also not >>> much rationale in commit msg for that. >> >> The main goal is to avoid choosing multiple IP addresses for erreta. >> If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA. > > Not explained in commit msg but anyway not a good argument. It is some > sort of micro optimization and you completely miss the point we target > multiarch kernels. Heh, and I actually did not forbid or discourage choosing erratas per your soc. I said you only get one top level ARCH. Look at all arm64 platforms. How many ARCHs are there per one vendor? Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 14:48 ` Krzysztof Kozlowski @ 2025-11-08 16:23 ` Conor Dooley 2025-11-08 16:32 ` Han Gao 0 siblings, 1 reply; 12+ messages in thread From: Conor Dooley @ 2025-11-08 16:23 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: revy, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, krzk+dt, conor+dt, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, geert+renesas, Guodong Xu, Haylen Chu, Joel Stanley, linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao [-- Attachment #1.1: Type: text/plain, Size: 3251 bytes --] On Sat, Nov 08, 2025 at 03:48:18PM +0100, Krzysztof Kozlowski wrote: > On 08/11/2025 15:47, Krzysztof Kozlowski wrote: > > On 08/11/2025 14:59, revy wrote: > >> > >> > >> > >>> -----Original Messages----- > >>> From: "Krzysztof Kozlowski" <krzk@kernel.org> > >>> Sent Time: 2025-11-08 19:29:07 (Saturday) > >>> To: gaohan@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alex@ghiti.fr>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>, "Jernej Skrabec" <jernej.skrabec@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Yixun Lan" <dlan@gentoo.org>, "Drew Fustini" <fustini@kernel.org>, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Guodong Xu" <guodong@riscstar.com>, "Haylen Chu" <heylenay@4d2.org>, "Joel Stanley" <joel@jms.id.au> > >>> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" <rabenda.cn@gmail.com> > >>> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu > >>> > >>> On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: > >>>> From: Han Gao <gaohan@iscas.ac.cn> > >>>> > >>>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, > >>>> using different IPs. > >>>> > >>>> d1(s): Xuantie C906 > >>>> v821: Andes A27 + XuanTie E907 > >>>> v861/v881: XuanTie C907 > >>>> > >>>> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> > >>>> --- > >>>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- > >>>> 1 file changed, 17 insertions(+), 5 deletions(-) > >>>> > >>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > >>>> index 848e7149e443..7cba5d6ec4c3 100644 > >>>> --- a/arch/riscv/Kconfig.socs > >>>> +++ b/arch/riscv/Kconfig.socs > >>>> @@ -54,14 +54,26 @@ config SOC_STARFIVE > >>>> help > >>>> This enables support for StarFive SoC platform hardware. > >>>> > >>>> -config ARCH_SUNXI > >>>> - bool "Allwinner sun20i SoCs" > >>>> +menuconfig ARCH_SUNXI > >>>> + bool "Allwinner RISC-V SoCs" > >>>> + > >>>> +if ARCH_SUNXI > >>>> + > >>>> +config ARCH_SUNXI_XUANTIE > >>> > >>> > >>> You should not get multiple ARCHs. ARCH is only one. There is also not > >>> much rationale in commit msg for that. > >> > >> The main goal is to avoid choosing multiple IP addresses for erreta. > >> If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA. > > > > Not explained in commit msg but anyway not a good argument. It is some > > sort of micro optimization and you completely miss the point we target > > multiarch kernels. > > Heh, and I actually did not forbid or discourage choosing erratas per > your soc. I said you only get one top level ARCH. Look at all arm64 > platforms. How many ARCHs are there per one vendor? Yeah, it only allows you to enable the errata, it doesn't force any of them to "y". Some will get enabled by default when ARCH_SUNXI is enabled, but if someone is only targeting on device they can just turn them off... I'm pretty inclined to just NAK this unless there's some actual value. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu 2025-11-08 16:23 ` Conor Dooley @ 2025-11-08 16:32 ` Han Gao 0 siblings, 0 replies; 12+ messages in thread From: Han Gao @ 2025-11-08 16:32 UTC (permalink / raw) To: Conor Dooley Cc: Han Gao, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, krzk+dt, conor+dt, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, geert+renesas, Guodong Xu, Haylen Chu, Joel Stanley, linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao > On Nov 9, 2025, at 00:23, Conor Dooley <conor@kernel.org> wrote: > > On Sat, Nov 08, 2025 at 03:48:18PM +0100, Krzysztof Kozlowski wrote: >> On 08/11/2025 15:47, Krzysztof Kozlowski wrote: >>> On 08/11/2025 14:59, revy wrote: >>>> >>>> >>>> >>>>> -----Original Messages----- >>>>> From: "Krzysztof Kozlowski" <krzk@kernel.org> >>>>> Sent Time: 2025-11-08 19:29:07 (Saturday) >>>>> To: gaohan@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alex@ghiti.fr>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>, "Jernej Skrabec" <jernej.skrabec@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Yixun Lan" <dlan@gentoo.org>, "Drew Fustini" <fustini@kernel.org>, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Guodong Xu" <guodong@riscstar.com>, "Haylen Chu" <heylenay@4d2.org>, "Joel Stanley" <joel@jms.id.au> >>>>> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" <rabenda.cn@gmail.com> >>>>> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu >>>>> >>>>> On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: >>>>>> From: Han Gao <gaohan@iscas.ac.cn> >>>>>> >>>>>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, >>>>>> using different IPs. >>>>>> >>>>>> d1(s): Xuantie C906 >>>>>> v821: Andes A27 + XuanTie E907 >>>>>> v861/v881: XuanTie C907 >>>>>> >>>>>> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> >>>>>> --- >>>>>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- >>>>>> 1 file changed, 17 insertions(+), 5 deletions(-) >>>>>> >>>>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >>>>>> index 848e7149e443..7cba5d6ec4c3 100644 >>>>>> --- a/arch/riscv/Kconfig.socs >>>>>> +++ b/arch/riscv/Kconfig.socs >>>>>> @@ -54,14 +54,26 @@ config SOC_STARFIVE >>>>>> help >>>>>> This enables support for StarFive SoC platform hardware. >>>>>> >>>>>> -config ARCH_SUNXI >>>>>> - bool "Allwinner sun20i SoCs" >>>>>> +menuconfig ARCH_SUNXI >>>>>> + bool "Allwinner RISC-V SoCs" >>>>>> + >>>>>> +if ARCH_SUNXI >>>>>> + >>>>>> +config ARCH_SUNXI_XUANTIE >>>>> >>>>> >>>>> You should not get multiple ARCHs. ARCH is only one. There is also not >>>>> much rationale in commit msg for that. >>>> >>>> The main goal is to avoid choosing multiple IP addresses for erreta. >>>> If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA. >>> >>> Not explained in commit msg but anyway not a good argument. It is some >>> sort of micro optimization and you completely miss the point we target >>> multiarch kernels. >> >> Heh, and I actually did not forbid or discourage choosing erratas per >> your soc. I said you only get one top level ARCH. Look at all arm64 >> platforms. How many ARCHs are there per one vendor? > > > Yeah, it only allows you to enable the errata, it doesn't force any of > them to "y". Some will get enabled by default when ARCH_SUNXI is > enabled, but if someone is only targeting on device they can just turn > them off... I'm pretty inclined to just NAK this unless there's some > actual value. I understand. I'm going to abandon this patch and plan to resubmit a patch that only modifies the description from sun20i to allwinnner. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE 2025-11-08 8:20 [PATCH 0/3] riscv: soc: re-organized allwinner gaohan 2025-11-08 8:20 ` [PATCH 1/3] riscv: soc: re-organized allwinner menu gaohan @ 2025-11-08 8:20 ` gaohan 2025-11-08 8:20 ` [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES gaohan 2025-11-08 9:46 ` [PATCH 0/3] riscv: soc: re-organized allwinner Jernej Škrabec 3 siblings, 0 replies; 12+ messages in thread From: gaohan @ 2025-11-08 8:20 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Han Gao, Yixun Lan, Drew Fustini, Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao From: Han Gao <gaohan@iscas.ac.cn> d1(s) use Xuantie IP. Signed-off-by: Han Gao <gaohan@iscas.ac.cn> --- arch/riscv/boot/dts/allwinner/Makefile | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile index 1c91be38ea16..635762ba06fe 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-clockworkpi-v3.14.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-devterm-v3.14.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-dongshan-nezha-stu.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv-86-panel-480p.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv-86-panel-720p.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv-dock.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-mangopi-mq-pro.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-nezha.dtb +dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1s-mangopi-mq.dtb -- 2.47.3 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES 2025-11-08 8:20 [PATCH 0/3] riscv: soc: re-organized allwinner gaohan 2025-11-08 8:20 ` [PATCH 1/3] riscv: soc: re-organized allwinner menu gaohan 2025-11-08 8:20 ` [PATCH 2/3] riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE gaohan @ 2025-11-08 8:20 ` gaohan 2025-11-08 11:29 ` Krzysztof Kozlowski 2025-11-08 9:46 ` [PATCH 0/3] riscv: soc: re-organized allwinner Jernej Škrabec 3 siblings, 1 reply; 12+ messages in thread From: gaohan @ 2025-11-08 8:20 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Han Gao, Yixun Lan, Drew Fustini, Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao From: Han Gao <gaohan@iscas.ac.cn> These options need to be enabled to prepare for v821/v861/v881. Signed-off-by: Han Gao <gaohan@iscas.ac.cn> --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc2725cbca18..ed0ac65babdc 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -29,6 +29,8 @@ CONFIG_ARCH_SOPHGO=y CONFIG_ARCH_SPACEMIT=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUNXI_XUANTIE=y +CONFIG_ARCH_SUNXI_ANDES=y CONFIG_ARCH_THEAD=y CONFIG_ARCH_VIRT=y CONFIG_ARCH_CANAAN=y -- 2.47.3 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES 2025-11-08 8:20 ` [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES gaohan @ 2025-11-08 11:29 ` Krzysztof Kozlowski 0 siblings, 0 replies; 12+ messages in thread From: Krzysztof Kozlowski @ 2025-11-08 11:29 UTC (permalink / raw) To: gaohan, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Yixun Lan, Drew Fustini, Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote: > From: Han Gao <gaohan@iscas.ac.cn> > > These options need to be enabled to prepare for v821/v861/v881. > > Signed-off-by: Han Gao <gaohan@iscas.ac.cn> > --- > arch/riscv/configs/defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index fc2725cbca18..ed0ac65babdc 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -29,6 +29,8 @@ CONFIG_ARCH_SOPHGO=y > CONFIG_ARCH_SPACEMIT=y > CONFIG_SOC_STARFIVE=y > CONFIG_ARCH_SUNXI=y > +CONFIG_ARCH_SUNXI_XUANTIE=y > +CONFIG_ARCH_SUNXI_ANDES=y No. One ARCH. You do not need more. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/3] riscv: soc: re-organized allwinner 2025-11-08 8:20 [PATCH 0/3] riscv: soc: re-organized allwinner gaohan ` (2 preceding siblings ...) 2025-11-08 8:20 ` [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES gaohan @ 2025-11-08 9:46 ` Jernej Škrabec 3 siblings, 0 replies; 12+ messages in thread From: Jernej Škrabec @ 2025-11-08 9:46 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Samuel Holland, Han Gao, Yixun Lan, Drew Fustini, Geert Uytterhoeven, Guodong Xu, Haylen Chu, Joel Stanley, gaohan Cc: linux-riscv, linux-kernel, devicetree, linux-arm-kernel, linux-sunxi, Han Gao Hi, Dne sobota, 8. november 2025 ob 09:20:22 Srednjeevropski standardni čas je gaohan@iscas.ac.cn napisal(a): > From: Han Gao <gaohan@iscas.ac.cn> > > Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, > using different IPs. > > d1(s): Xuantie C906 > v821: Andes A27 + XuanTie E907 > v861/v881: XuanTie C907 > > Han Gao (3): > riscv: soc: re-organized allwinner menu > riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE > riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES This series is incomplete. It introduces ARCH_SUNXI_ANDES symbol but it is never used. Additionally, patches are not organized properly. First, you should introduce reorganization and only then introduce new features. Also, not a single patch should break existing functionality for bisectability reasons. First patch breaks compilation of DT files while second restores that. This must not happen. Best regards, Jernej > > arch/riscv/Kconfig.socs | 22 +++++++++++++++++----- > arch/riscv/boot/dts/allwinner/Makefile | 20 ++++++++++---------- > arch/riscv/configs/defconfig | 2 ++ > 3 files changed, 29 insertions(+), 15 deletions(-) > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-11-08 16:32 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-08 8:20 [PATCH 0/3] riscv: soc: re-organized allwinner gaohan 2025-11-08 8:20 ` [PATCH 1/3] riscv: soc: re-organized allwinner menu gaohan 2025-11-08 11:29 ` Krzysztof Kozlowski 2025-11-08 13:59 ` revy 2025-11-08 14:47 ` Krzysztof Kozlowski 2025-11-08 14:48 ` Krzysztof Kozlowski 2025-11-08 16:23 ` Conor Dooley 2025-11-08 16:32 ` Han Gao 2025-11-08 8:20 ` [PATCH 2/3] riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE gaohan 2025-11-08 8:20 ` [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES gaohan 2025-11-08 11:29 ` Krzysztof Kozlowski 2025-11-08 9:46 ` [PATCH 0/3] riscv: soc: re-organized allwinner Jernej Škrabec
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