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Tue, 30 Jun 2026 21:21:09 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.232]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ca37c73a9csm24450865ad.21.2026.06.30.21.20.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 30 Jun 2026 21:21:08 -0700 (PDT) From: Yunhui Cui To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, eddyz87@gmail.com, memxor@gmail.com, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, bjorn@kernel.org, pulehui@huawei.com, puranjay@kernel.org, thuth@redhat.com, ajones@ventanamicro.com, ben.dooks@codethink.co.uk, rkrcmar@ventanamicro.com, cuiyunhui@bytedance.com, samuel.holland@sifive.com, zong.li@sifive.com, conor.dooley@microchip.com, tglx@kernel.org, debug@rivosinc.com, seanwascoding@gmail.com, andybnac@gmail.com, menglong8.dong@gmail.com, cyrilbur@tenstorrent.com, wangruikang@iscas.ac.cn, atishp@rivosinc.com, apatel@ventanamicro.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, bpf@vger.kernel.org, arnd@arndb.de, nathan@kernel.org, nick.desaulniers+lkml@gmail.com, morbo@google.com, justinstitt@google.com, qingfang.deng@siflower.com.cn, linux-arch@vger.kernel.org, llvm@lists.linux.dev Subject: [PATCH v5 0/3] riscv: improve percpu helpers and PIO mapping Date: Wed, 1 Jul 2026 12:20:38 +0800 Message-Id: X-Mailer: git-send-email 2.39.2 (Apple Git-143) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260630_212111_535863_89B4A0F0 X-CRM114-Status: UNSURE ( 8.37 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Changes in v5: - Keep the PIO helper fix local to RISC-V: drop the generic HAS_IOPORT_MAP dependency change and the generic ioport_map() change from v4. - Add the missing linux/bits.h include for GENMASK and BITS_PER_BYTE. - Fix the 8/16-bit LR/SC fallback to mask subword results before writing them back. - Use early-clobber constraints in the 8/16-bit add_return LR/SC fallback. - Fix this_cpu_and_4/8 to pass the intended operand to RISC-V amoand. - Initialize the secondary idle task pcpu_offset before starting the CPU. Yunhui Cui (3): riscv: io: avoid null-pointer arithmetic in PIO helpers riscv: introduce percpu.h into include/asm riscv: store percpu offset into thread_info arch/riscv/include/asm/asm.h | 6 +- arch/riscv/include/asm/io.h | 26 ++- arch/riscv/include/asm/percpu.h | 287 +++++++++++++++++++++++++++ arch/riscv/include/asm/switch_to.h | 8 + arch/riscv/include/asm/thread_info.h | 3 +- arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/smpboot.c | 8 + arch/riscv/net/bpf_jit_comp64.c | 9 +- 8 files changed, 326 insertions(+), 22 deletions(-) create mode 100644 arch/riscv/include/asm/percpu.h -- 2.39.5 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv