From: William Qiu <william.qiu@starfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
"Emil Renner Berthing" <kernel@esmil.dk>
Subject: Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc
Date: Mon, 20 Mar 2023 15:32:14 +0800 [thread overview]
Message-ID: <d0b1d44e-6d6e-536c-046e-be6a53f1d240@starfivetech.com> (raw)
In-Reply-To: <f25cc55e-3405-4b17-fb45-5ae5eb36a404@linaro.org>
On 2023/3/20 14:38, Krzysztof Kozlowski wrote:
> On 20/03/2023 06:54, William Qiu wrote:
>>
>>
>> On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
>>> On 15/03/2023 06:58, William Qiu wrote:
>>>> Add documentation to describe StarFive System Controller Registers.
>>>>
>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>> ---
>>>> .../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
>>>> MAINTAINERS | 5 +++
>>>> 2 files changed, 46 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> new file mode 100644
>>>> index 000000000000..ae7f1d6916af
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> @@ -0,0 +1,41 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive JH7110 SoC system controller
>>>> +
>>>> +maintainers:
>>>> + - William Qiu <william.qiu@starfivetech.com>
>>>> +
>>>> +description: |
>>>> + The StarFive JH7110 SoC system controller provides register information such
>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + items:
>>>> + - enum:
>>>> + - starfive,jh7110-aon-syscon
>>>> + - starfive,jh7110-stg-syscon
>>>> + - starfive,jh7110-sys-syscon
>>>> + - const: syscon
>>>
>>> Does not look like you tested the bindings. Please run `make
>>> dt_binding_check` (see
>>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>>
>>> ... or your PLL clock controller was not tested.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Hi Krzysztof,
>>
>> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
>> was not tested which I didn't add in this patch series. And PLL clock controller belongs
>> to Xingyu Wu, I would tell him.
>
> What's confusing you do not allow here clock controller.
>
> Best regards,
> Krzysztof
>
I'll add it then.
Best regards
William
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next prev parent reply other threads:[~2023-03-20 7:32 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-15 5:58 [RESEND v6 0/2] StarFive's SDIO/eMMC driver support William Qiu
2023-03-15 5:58 ` [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc William Qiu
2023-03-15 19:00 ` Conor Dooley
2023-03-19 12:27 ` Krzysztof Kozlowski
2023-03-20 5:54 ` William Qiu
2023-03-20 6:38 ` Krzysztof Kozlowski
2023-03-20 7:32 ` William Qiu [this message]
2023-04-05 16:38 ` Conor Dooley
2023-04-06 2:20 ` William Qiu
2023-03-19 12:29 ` Krzysztof Kozlowski
2023-03-20 6:00 ` William Qiu
2023-03-20 6:38 ` Krzysztof Kozlowski
2023-03-20 7:31 ` William Qiu
2023-03-15 5:58 ` [RESEND v6 2/2] riscv: dts: starfive: Add syscon node William Qiu
2023-03-15 18:57 ` Conor Dooley
2023-03-15 21:03 ` Emil Renner Berthing
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