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Wed, 27 Sep 2023 13:24:24 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.9.0-alpha0-958-g1b1b911df8-fm-20230927.002-g1b1b911d MIME-Version: 1.0 Message-Id: In-Reply-To: <20230922085701.3164-3-yongxuan.wang@sifive.com> References: <20230922085701.3164-1-yongxuan.wang@sifive.com> <20230922085701.3164-3-yongxuan.wang@sifive.com> Date: Wed, 27 Sep 2023 13:24:03 -0400 From: "Stefan O'Rear" To: "Yong-Xuan Wang" , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, tjytimi@163.com, alex@ghiti.fr, "Conor Dooley" , "Rob Herring" , "Krzysztof Kozlowski" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Svadu Entry X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230927_102434_547512_E4D4D62C X-CRM114-Status: GOOD ( 17.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Sep 22, 2023, at 4:56 AM, Yong-Xuan Wang wrote: > Add an entry for the Svadu extension to the riscv,isa-extensions property. > > Signed-off-by: Yong-Xuan Wang > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml > b/Documentation/devicetree/bindings/riscv/extensions.yaml > index cc1f546fdbdc..b5a0aed0165b 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -147,6 +147,12 @@ properties: > ratified at commit 3f9ed34 ("Add ability to manually > trigger > workflow. (#2)") of riscv-time-compare. > > + - const: svadu > + description: | > + The standard Svadu supervisor-level extension for hardware updating > + of PTE A/D bits as frozen at commit b65e07c ("move to Frozen > + state") of riscv-svadu. > + This is incomplete without a specification of the behavior of the HADE bit implied by svadu being present. The ratified RVA20 requires page table accesses with A/D = 0 to trap, in other words HADE = 0 for RVA20 conformance. If we are serious about compatibility, I think that we need platforms to be able to conform to both RVA20 and RVA23, which requires HADE = 0 at kernel entry with a SBI call to set HADE = 1. For the same reason KVM should probably default to HADE = 0 so that the default configuration remains conformant to RVA20. -s > - const: svinval > description: > The standard Svinval supervisor-level extension for fine-grained > -- > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv